RTL for MIPS instructions Fall 2005 2006 add

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RTL for MIPS instructions Fall 2005 -2006

RTL for MIPS instructions Fall 2005 -2006

add 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

add 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]]; Sum = PC + SE[IR[15: 0]]<< 2 if((IR[31: 26] == 0) && (IR[5: 0] == 32)) then 3. Sum = A + B 4. Reg[IR[15: 11]] = Sum

lw 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

lw 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]]; Sum = PC + SE[IR[15: 0]]<< 2 if((IR[31: 26] == 35) then 3. Sum = A + SE[IR[15: 0]] 4. MDR = Mem[Sum] 5. Reg[IR[20: 16]] = MDR

sw 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

sw 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]] Sum = PC + SE[IR[15: 0]]<< 2 if((IR[31: 26] == 43) then 3. Sum = A + SE[IR[15: 0]]; B = Reg[IR[20: 16]] 4. Mem[Sum] = B

beq 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

beq 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]] Sum = PC + SE[IR[15: 0]]<< 2 ; if((IR[31: 26] == 4) then 3. If (A – B == 0) then PC = Sum

j 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

j 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]]; Sum = PC + SE[IR[15: 0]]<< 2 if((IR[31: 26] == 2) then 3. PC = PC[31: 28] || IR[25: 0] || 00

jal 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

jal 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]]; Sum = PC + SE[IR[15: 0]]<< 2 if((IR[31: 26] == 3) then 3. PC = PC[31: 28] || IR[25: 0] || 00 Reg[31] = PC

jr 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25:

jr 1. PC = PC + 4; IR = Mem[PC] 2. A = Reg[IR[25: 21]]; B = Reg[IR[20: 16]]; Sum = PC + SE[IR[15: 0]]<< 2 if((IR[31: 26] == 0 and IR[5: 0] == 8) 3. PC = A

Single-cycle datapath • Simple control unit (combinational logic) • The processor will be under-utilized

Single-cycle datapath • Simple control unit (combinational logic) • The processor will be under-utilized (idle during portions of the clock cycle for many instructions)

add PC = PC + 4 If ( (Mem[PC])[31: 26] == 0 && (Mem[PC])[5:

add PC = PC + 4 If ( (Mem[PC])[31: 26] == 0 && (Mem[PC])[5: 0]) == 32) then Reg[ (Mem[PC])[15: 11]] = Reg[(Mem[PC])[25: 21]] + Reg[(Mem[PC])[20: 16]]

lw PC = PC + 4 If ( (Mem[PC])[31: 26] == 35) then Reg[

lw PC = PC + 4 If ( (Mem[PC])[31: 26] == 35) then Reg[ (Mem[PC])[20: 16]] = Mem [ Reg [ (Mem[PC])[25: 21] + SE[(Mem)[PC][15: 0] ]

sw PC = PC+4 If((Mem[PC])[31: 26] == 43) then Mem[Reg[(Mem[PC])[25: 21]] + SE[(Mem[PC]) [15:

sw PC = PC+4 If((Mem[PC])[31: 26] == 43) then Mem[Reg[(Mem[PC])[25: 21]] + SE[(Mem[PC]) [15: 0]] ] = Reg[ (Mem[PC])[20: 16]]

beq PC = PC + 4 If ( (Mem[PC])[31: 26] == 4) then if(

beq PC = PC + 4 If ( (Mem[PC])[31: 26] == 4) then if( (Reg[(Mem[PC])[25: 21]] – Reg[(Mem[PC])[20: 16]) == 0) then PC = PC + [SE[(Mem[PC])[15: 0] << 2]

j PC = PC + 4 If ( (Mem[PC])[31: 26] == 2) then PC

j PC = PC + 4 If ( (Mem[PC])[31: 26] == 2) then PC = PC[31: 28]|| (Mem[PC])[25: 0] || 00

lui PC = PC + 4 if((Mem[PC])[31: 26] == 0 xf) Reg[ (Mem[PC])[20: 16]

lui PC = PC + 4 if((Mem[PC])[31: 26] == 0 xf) Reg[ (Mem[PC])[20: 16] ] = (Mem[PC])[15: 0] << 16

addi PC = PC + 4 if((Mem[PC])[31: 26] == 0 x 8) Reg[ (Mem[PC])[20:

addi PC = PC + 4 if((Mem[PC])[31: 26] == 0 x 8) Reg[ (Mem[PC])[20: 16] ] = Reg[ (Mem[PC])[25: 21] ] + SE[ (Mem[PC])[15: 0] ]

RTL for MIPS instructions Fall 2005 2006 addRTL for MIPS instructions Fall 2005 2006 add
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MIPS Processor Registers in MIPS In MIPS thereMIPS Processor Registers in MIPS In MIPS there
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MIPS ver 2 public class MIPS public MIPSMIPS ver 2 public class MIPS public MIPS
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Pseudo instructions Pseudo instructions MIPS supports pseudo instructionsPseudo instructions Pseudo instructions MIPS supports pseudo instructions
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Pseudo instructions Pseudo instructions MIPS supports pseudo instructionsPseudo instructions Pseudo instructions MIPS supports pseudo instructions
Pseudo instructions Pseudo instructions MIPS supports pseudo instructionsPseudo instructions Pseudo instructions MIPS supports pseudo instructions
ABCN 130 RTL status Running functional rtl codeABCN 130 RTL status Running functional rtl code
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