Exercise 2 RTL Lab 4 v module lab

Exercise 2

RTL • Lab 4. v module lab 4 (nibble 1, nibble 2, byte_out, clk, reset); input [3: 0] nibble 1, nibble 2; input clk, reset; output [7: 0] byte_out; reg [7: 0] byte_out, stored 3, stored 2, stored 1, stored 0; always @ (posedge clk or posedge reset) if (reset) begin byte_out <= 0; stored 3 <= 0; stored 2 <= 0; stored 1 <= 0; stored 0 <= 0; end else begin // Shift nibble by padding with zeroes. MSB must be zero to make // the size of the left-hand side match the set size of the // right-hand side. stored 3 stored 2 stored 1 stored 0 byte_out endmodule <= <= nibble 1[3] ? {1'b 0, nibble 2[3: 0], 3'b 0} : 8'b 0; <= nibble 1[2] ? {2'b 0, nibble 2[3: 0], 2'b 0} : 8'b 0; <= nibble 1[1] ? {3'b 0, nibble 2[3: 0], 3'b 0} : 8'b 0; <= nibble 1[0] ? {4'b 0, nibble 2[3: 0]} : 8'b 0; stored 3 + stored 2 + stored 1 + stored 0;

Test-bench File module tb; reg clk, reset; reg[3: 0] nibble 1, nibble 2; wire[7: 0] result; lab 4 inst 1(nibble 1, nibble 2, result, clk, reset); initial begin clk=0; reset=1; #5 reset=0; nibble 1=5; nibble 2=7; #30; $finish; end always #10 clk=~clk; initial $monitor(“clk=%b reset=%b nibble 1=%d nibble 2=%d byte_out=%d", clk, reset, nibble 1, nibble 2, result); endmodule

UCF File NET clk LOC=T 9; NET reset LOC=L 14; :

NOTES • Switch 1 used for reset signal

Steps • • • Key in Synthesis by ISE Simulate the design by Model. Sim What is the function of Lab 4. v? Add the circuit that can use LED to displays the result – Design a binary-to-BCD converter and a 7 -segment decoder • Reference: http: //216. 239. 51. 100/search? q=cache: SNo. Uid. Ob. Gus. C: www. eng. utsa. edu/~ppatel/Xilinx%2520 Tutori al 2. htm+BCD+decoder+7+verilog&hl=zh-TW&ie=UTF-8 – Implement the enhanced design by Starter Kit