Feedback and State 1 ROMs 2 Latches and

Feedback and State 1. ROMs 2. Latches and Flip-Flops Handouts: Lecture Slides 1

General Purpose “Table-Lookup” Device a. k. a Read-Only Memory (ROM) Decoder A B Cin Fixed “AND plane” 0 1 2 3 4 5 6 7 S This ROM stores 16 bits in 8 words of 2 bits. Configurable “OR plane” Cout Configurable Selector Made from PREWIRED connections , and CONFIGURABLE connections that can be either connected or not connected 2

ROM Implementation Technology A PFET with gate tied to ground = resistor pullup that makes wire “ 1” unless one of the NFET pulldowns is on. Hardwired AND logic Programmable OR logic B Advantages: - Very regular design Cin S Cout Problems: - Active Pull-ups (Static Power) - Long metal wires, large capacitance - Slow 3

Speeding up ROMs 000 Minimize the capacitances of those long wires running through the array. 001 010 011 The best way to accomplish this is to build square arrays: 100 101 00 110 01 111 A B CIN S COUT 10 A B CIN 2 D Addressing: Standard for ROMs, RAMs, … 11 0 1 S 0 COUT 1 4

Example: 7 -sided Die We want to construct a readout displaying the following symbols: An array of LEDs, labeled as follows, can be used to display the outcome of the die: T V Y U W X Z 5

ROM-Based Design Truth Table for a 7 -sided Die • Once we’ve written out the truth table we’ve basically finished the design • Possible optimizations: • - Eliminate redundant outputs • - Addressing tricks T V Y U W X Z 6

A Simple ROM implementation A B C T V No output depends on this product term U W Y T/Z U/Y V/X W X Z That was easy but there is clearly some waste. - unused products - over-specified terms 7

Digital State One model of what we’d like to build Next State Memory Device LOAD Current State Combinational Logic Input Output Plan: Build a Sequential Circuit with stored digital STATE – • Memory stores CURRENT state, produced at device output • Combinational Logic computes • Next state (from input, current state) • Output bit (from input, current state) • State changes on LOAD control input 8

Memory/Storage Device Using Feedback IDEA: use positive feedback to maintain storage indefinitely. VOUT VIN VTC for Feedback constraint: inverter pair VIN = VOUT Result: a bistable storage element Not affected by noise Three solutions: w two end-points are stable w middle point is unstable VIN We’ll get back to this! 9

Settable Storage Element It’s easy to build a settable storage element (called a latch) using a MUX: “state” signal appears as both input and output A G D QIN QOUT 0 Q Y D B S G 1 0 0 1 1 --0 1 --- 0 1 Q stable Q follows D 10

New Device: D Latch G=1: Q follows D Q’ 0 D 1 D Q V 1 G=0: Q holds V 2 G G D Q Q V 1 tpd V 2 tpd G G=1: Q Follows D, independently of Q’ G=0: Q Holds stable Q’, independently of D 11

Hazardous D-Latch Qold = 1 initially Y Q G D=1 “glitch” or “hazard” Z Only one input G changes to latch Glitch at Q can cause Y to fall and change state Want Q to stay at 1 12

Lenient D-latch D DG G Q GQ DQ 1 GQ 00 D 0 0 01 11 1 0 0 0 1 1 10 No problem for all single input transitions What if D and G change 1 0 at the same time? 13

Timing Specifications for D-Latch D Q G tpd G Q tcd G Q Flow through Setup time = ts Hold time = th ts th G D Q old Q D must not change in this region to ensure single input change to latch 14

Dynamic Discipline for Latch D Stable tpd Q’ A 0 D 1 Q Y G To reliably latch V 2: • Apply V 2 to D, holding G=1 • After tpd, V 2 appears at Q=Q’ • After another tpd, Q’ & D both valid for tpd; will hold Q=V 2 independently of G • Set G=0, while Q’ & D hold D=Q • After another tpd, G=0 and Q’ are sufficient to hold Q=V 2 independently of D D V 2 G Q V 2 tpd tpd tsetup thold Dynamic Discipline for Latch tsetup = 2 tpd: interval prior to G transition for which D must be stable & valid thold = tpd: interval following G transition for which D must be stable & valid 15

Latch-Based Sequential Circuit Next State D Q G Current State Combinational Logic Input Output Plan: Build a Sequential Circuit with one bit of STATE – • Single latch holds CURRENT state • Combinational Logic computes • Next state (from input, current state) • Output bit (from input, current state) • State Q changes when G = 1 16

Combinational Cycles New State D Q 1 G Current State Combinational Logic Input Output When G=1, latch is Transparent… … provides a combinational path from D to Q. Need a G=1 PULSE for this to work! Pulse too wide combinational cycle Pulse too narrow not enough time for D to change Q Two-sided time bounds make this virtually unimplementable 17

Flaky Control Systems Here’s a strategy for saving a few bucks on the Pike 18

Edge-triggered Flip Flop The gate of this latch is open when the clock D CLK is low D Q master slave G G Q The gate of this latch is open when the clock D D Q Q CLK is high Observations: w only one latch “transparent” at any time: w master closed when slave is open w slave closed when master is open no combinational path through flip flop w Q only changes shortly after 0 1 transition of CLK, so flip flop appears to be “triggered” by rising edge of CLK 19

Latches and Flip-Flops D Q is like a toll-gate G D Q is like an air-lock 20

Discrete-Time Sequential Circuit No combinational cycle! Flip. Flop Clock Current State New State Combinational Logic Input Output Active Clock Edges punctuate time -- • Discrete Clock periods, state variables, specifications • Dynamic discipline for flip-flop corresponds to various timing constraints 21

Next Time: Clocking Dilbert : S. Adams 22