FlipFlops Latches Digital Electronics FlipFlops Latches This presentation
- Slides: 27
Flip-Flops & Latches Digital Electronics
Flip-Flops & Latches This presentation will: • Review sequential logic and the flip-flop. • Introduce the D flip-flop and provide an excitation table and a sample timing analysis. • Introduce the J/K flip-flop and provide an excitation table and a sample timing analysis. 2
Flip-Flops & Latches This presentation will: • Review flip-flop clock parameters. • Introduce the transparent D-latch. • Discuss flip-flop asynchronous inputs. 3
Sequential Logic & The Flip-Flop Inputs . . Combinational . . Outputs Logic Gates Clock Memory Elements (Flip-Flops) 4
D Flip-Flop: Excitation Table D CLK Q D CLK 0 0 1 1 1 0 : Rising Edge of Clock 5
D Flip-Flop: Example Timing Q=D=0 Q=D=1 Q=D=0 No Change Q=D=0 Q=D=1 No Change Q=D=0 No Change Q D CLK 6
J/K Flip-Flop: Excitation Table J Q CLK K J K CLK 0 0 0 1 0 Clear 1 0 1 Set 1 1 No Change Toggle : Rising Edge of Clock 7
J/K Flip-Flop: Example Timing TOGGLE SET CLEAR TOGGLE NO CHANGE SET NO CHANGE Q J K CLK 8
Clock Edges Positive Edge Transition 1 0 Negative Edge Transition 9
POS & NEG Edge Triggered D Positive Edge Trigger D CLK Q D CLK 0 0 1 1 1 0 : Rising Edge of Clock 10
POS & NEG Edge Triggered D Negative Edge Trigger D CLK Q D CLK 0 0 1 1 1 0 : Falling Edge of Clock 11
POS & NEG Edge Triggered J/K Positive Edge Trigger J Q CLK K J K CLK 0 0 0 1 0 1 1 1 : Rising Edge of Clock 12
POS & NEG Edge Triggered J/K Negative Edge Trigger Q J CLK K J K CLK 0 0 0 1 0 1 1 1 : Falling Edge of Clock 13
Flip-Flop Timing Data Input (D, J, or K) Positive Edge Clock 1 0 t. S t. H Setup Time Hold Time 1 0 Setup Time (t. S): The time interval before the active transition of the clock signal during which the data input (D, J, or K) must be maintained. 14
Flip-Flop Timing Data Input (D, J, or K) Positive Edge Clock 1 0 t. S t. H Setup Time Hold Time 1 0 Hold Time (t. H): The time interval after the active transition of the clock signal during which the data input (D, J, or K) must be maintained. 15
Asynchronous Inputs Asynchronous inputs (Preset & Clear) are used to override the clock/data inputs and force the outputs to a predefined state. The Preset (PR) input forces the output to: PR D Q CLK CLR The Clear (CLR) input forces the output to: 16
Asynchronous Inputs PR D Q CLK PR CLK D PRESET CLEAR CLOCK DATA 1 1 0 0 1 X X 1 0 Asynchronous Preset 1 0 X X 0 1 Asynchronous Clear 0 0 X X 1 1 ILLEGAL CONDITION CLR 17
D Flip-Flop: PR & CLR Timing Q=D=1 Q=D=0 Clocked Q PR Q=D=0 Q=D=1 Q=D=0 Clocked Q=1 Preset Q=0 Clear CLR D CLK 18
Transparent D-Latch D EN Q EN D 0 X 1 0 0 1 1 0 EN: Enable 19
Transparent D-Latch: Example Timing “Transparent” Q=D “Latched” Q=D Q=1 Q=0 Q D EN 20
Flip-Flop Vs. Latch • The primary difference between a D flip-flop and D latch is the EN/CLOCK input. • The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop’s output changes on the edge (rising or falling) of the CLOCK input. • The latch’s EN input is level sensitive, meaning the latch’s output changes on the level (high or low) of the EN input. 21
Flip-Flops & Latches 74 LS 74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs 22
Flip-Flops & Latches 74 LS 76 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 23
Flip-Flops & Latches 74 LS 75 Quad Latch 24
74 LS 74: D Flip-Flop 25
74 LS 76: J/K Flip-Flop 26
74 LS 75: D Latch 27
- Counter digital electronics
- Latches
- Flipflops
- Difference between flip flop and latch
- What is the difference between latches and flip flops
- Conventional cmos latches
- Sr latch truth table
- D flip flop truth table
- Is camera electronic device
- Setup time and hold time in digital electronics
- Accumulator electronics
- Digital vs analog video
- Digital electronics question
- Ram digital electronics
- How to read capacitor value
- Boolean
- Number system in digital electronics
- Arithmetic building blocks
- 555 timer calculations
- Sequential programmable logic devices
- Timing diagram of xor gate
- Digital electronics chapter 1
- Weighted and non weighted codes with example
- De morgan
- The dtl propagation delay is relatively
- Number system digital electronics
- State machines digital electronics
- Prom pld