EEE 404591 RealTime Digital Signal Processing http lina

EEE 404/591 - Real-Time Digital Signal Processing http: //lina. faculty. asu. edu/realdsp/ Introduction Prof. Lina Karam School of Electrical, Computer & Energy Engineering Arizona State University karam@asu. edu Contributions by Dr. Rony Ferzli Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP

What is Signal Processing? Signal in Signal out Processing (Analog or Digital) Operation, Transformation § Example of Signals: Ø Ø Analog: Speech, Music, Photos, Video, radar, sonar, … Discrete-domain/Digital: ü ü digitized speech, digitized music, digitized images, digitized video, digitized radar and sonar signals, … stock market data, daily max temperature data, . . . Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 2

What is Digital Signal Processing? Digital Signal in Digital Processing Digital Signal out Operation, Transformation performed on digital signals (using a computer or other special-purpose digital hardware) § But what about analog signals? Analog Signal in Analog-to. Digital (A/D) Conversion Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP Digital Processing 3 Digital-to. Analog (D/A) Conversion

Typical Scenario Step 1: Analog sensor picking analog signal (e. g. , microphone picking sound) Step 2: Analog to Digital Converter Step 3: DSP processes the digital signals (e. g. , compression, noise suppression) Step 4: Digital to analog converter to recover the analog signal Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 4

What is Real-Time Digital Signal Processing? Digital Signal in § Example: Ø Real-Time Digital Processing Digital Signal out Time-constrained Operation or Transformation performed on digital signals within a required period of time to maintain synchronization with occurring events. Processor clocked at 120 MHz and can perform 120 MIPS ü ü ü Sampling rate = 48 KHz (Digital Audio Tape - DAT) number of instructions per sample = (120 x 106)/(48 x 103) = 2500. Sampling rate = 8 KHz (voice-band, telephony) number of instructions per sample = 15000. Sampling rate = 75 MHz (CIF 360 x 288 Video at 30 frames per second) number of instructions per sample = 1. 6. Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 5

Real-Time Digital Signal Processing § Constraints: Ø § real-time DSP applications limited to cases where the required sampling rate is sufficiently lower than the processor’s instruction rate Challenge: Ø Ø Ø Produce working code. Produce sufficiently compact code to execute in real -time. A sufficient number of instructions need to be performed between sample periods. Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 6

What is DSP? § § DSP = Digital Signal Processing OR DSP = Digital Signal Processor? DSP used to denote both Ø § meaning can be deduced from the context in which the term DSP is used. What is a Digital Signal Processor (DSP)? Ø Microprocessor specifically designed to perform fast DSP operations (e. g. , Fast Fourier Transforms, inner products, Multiply & Accumulate) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 7

Why Go Digital? § Programmability Ø Ø § Repeatability Ø Ø § § One hardware can perform several tasks. Upgradeability and flexibility. Identical performance from unit to unit. No drift in performance due to temperature or aging. Immune to noise Offers higher performance : CD players versus phonographic turntable Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 8

Signal Processing Applications § Speech processing Ø Ø Ø § Speech compression Speech recognition Speaker Identification, Verification Speech synthesis Speech enhancement, Echo cancellation Audio Processing Ø Ø Compression 3 -D reproduction Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 9

DSP Applications – Image Processing § Image Processing Ø Ø Ø Ø § Image compression Pattern recognition Ghost cancellation Noise reduction Deblurring Object tracking Image fusion Video Processing/compression, tracking. . . Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 10

DSP Applications Communications § MODEM Ø Ø Ø § Cellular Telephony Ø Ø Ø § correlators (matched filters) echo cancellers equalizers speech compression diversity combining array processing Software Radio Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 11

DSP Targets: Cell Phone Controlled by Power Management Unit RF Microprocessor Cell Receiver Chip Peripherals RF DSP Codec Chip Voice Codec -Speech Coders -Speech Recognition - Equalizers - Antenna noise cancellation -Image enhancement techniques Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 12

DSP Targets: Cell Phone Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 13

DSP Targets: Voice Over IP Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 14

DSP Targets: PORTABLE MEDIA DEVICES Audio Coding Speech Recognition Image Compression Image enhancement Source: Texas Instruments Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 15

DSP Market – Ranking 2011 Revenue (in Billions of Dollars) 16 14 12 10 8 6 4 2 0 TI Freescale Analog Devices NXP (Philips Semiconductor) LSI (Agere) DSP Group Kits available in the lab are from TI and Freescale Ranking: • Texas Instruments • Freescale Semiconductor • NXP • Analog Devices • LSI (Agere) • DSP Group Ref: http: //investor. ti. com/fininfo. cfm www. freescale. com www. analog. com http: //www. nxp. com www. lsi. com www. ir. dspg. com Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 16

DSP Market – By Application Communications applications (e. g. , wireless) Jumped from 11, 000 Million $ in 2008 to 17, 000 Million $ in 2012. Ref: Forward Concepts http: //www. fwdconcepts. com/Pages/press 42. htm DSP History: https: //fwdconcepts. com/wireless-and-dsp-resources/dsp-history/ Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 17

Portable Applications § Embedded signal and image processing tasks are becoming more demanding Ø Ø Ø § § § Wireless communications (e. g. , 4 G/LTE, UWB): higher data rates, more complex systems and air interfaces Video processing (HDTV, UHDTV, Camcorders, 3 DTV): compression, decompression, enhancement, superresolution, feature extraction Still image processing: cameras, copiers, printers, imagebased rendering High performance is required: 100 s to 1000 s of GOP High efficiency: 100 s of MOPS/m. W (GOPS/m. W), 10 s GOPS/$ Programmability: multiple modes, evolving standards, evolving features Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 18

What is Special about Signal Processing Applications? § § Large number of samples being continuously fed to the system (samples or blocks). Repetitive Operations: Ø Ø § § The same operation being applied to different set of samples Parallel processing Vector and Matrix Operations Real time operations Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 19

Example: Digital Filtering § The two most common real-time digital filters are: Ø Ø § Finite Impulse Filter (FIR) Infinite Impulse Filter (IIR) The basic FIR Filter equation is where h[k] is an array of constants y[n]=0; For (n=0; n<N; n++) In C language { For (k = 0; k<N; k++) //inner loop y[n] = y[n] + h[k]*x[n-k]; } Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 20 Only Multiply and Accumulate (MAC) is needed!

MAC using General Purpose Processor (GPP) R 0 11 12 3 11 24 X R 1 1 9 2 3 Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP R 2 44 Loop Clr A ; Clear Accumulator A Clr B ; Clear Accumulator B Mov *R 0, Y 0 ; Move data from memory location 1 to register Y 0 Mov *R 1, X 0 ; Move data from memory location 2 to register X 0 Mpy X 0, Y 0, A ; X 0*Y 0 ->A Add A, B ; A + B -> B Inc R 0 ; R 0 + 1 -> R 0 Inc R 1 ; R 1 + 1 -> R 1 Dec N ; Dec N (initially equals to 3) Tst N ; Test for the value Jnz Loop ; Different than zero loop again Mov B, *R 2 ; Move result to memory 21

MAC using DSP 11 12 3 11 R 2 44 24 X 1 9 2 3 Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP Clr A ; Clear Accumulator A Rep N ; Rep N times the next instruction MAC *(R 0)+, *(R 1)+, A ; Fetch the two memory locations pointed by R 0 and R 1, multiply them together and add the result to A, the final result is stored back in A Mov A, *R 2 ; Move result to memory 22

Digital Signal Processors – Data Path Only Program Memory Data Bus Data Memory Data Bus Program Memory § § § Data Memory A DSP Chip is a microprocessor specially designed for DSP applications Harvard architecture allows multiple memory reads Architecture optimized to provide rapid processing of discrete time signals, e. g. Multiply and Accumulate (MAC) in one cycle Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP Multiplexer ALU Accumulator 23

Memory structures Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 24

DSP Features § Multiple parallel units Ø Ø Ø § Memory Access Ø Ø Ø § special ALU for address calculation Bit reversed addressing circular addressing Automatic loops Ø Ø § multiply accumulate (possibly several units) address calculation in parallel to processing barrel shifter Software looping: writing assembly code to perform branching Hardware looping: dedicated hardware loop counter register Hardware support for managing arithmetic computation (in GPP it needs multiple cycles) Ø Ø Ø Shifters Guard bits Saturation Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP Preventing Overflow!! 25

Digital Signal Processor (DSP) - Overview § § DSP Core includes: Ø Address buses Ø Data arithmetic logic unit (ALU) Data memory Ø Address generation unit (AGU) On-chip Peripherals Ø Program controller Ø Bit-manipulation unit Ø Enhanced debugging module Peripherals on chip Ø Timer DM Ø serial link Ø communication links Core ü DSP to DSP PM ü Ethernet ü ATM Ø host ports Ø input/output pins Adaptation for FFT Ø bit reverse addressing Program Memory Special instructions Ø Parallel move support Ø Loop instructions; special hardware instructions (e. g. , FIR) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 26

Enhancing DSP Architectures § More parallelism Ø Increase the number of operations that can be performed in each instruction ü Ø § § § Adding More Executing units (e. g. , Multipliers) Increase the number of instructions that can be issued and executed in every cycle Highly specialized hardware in core Co-processors Multi-Core DSPs Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 27

Example: TI OMAP Chip § § § Integrates a TMS 320 C 55 x™ DSP core with an ARM GPP on a Single Chip Targeted for embedded applications ARM interfacing peripherals: Ø Ø § C 55 x to perform DSP algorithms Ø Ø Ø § Bluetooth Ir. DA Keypad Touch Screen Mobile Messaging Handwriting Recognition Digital Cameras Image processing OMAP 2 Architecture includes a dedicated Ø Ø Image and video accelerator 3 D graphics accelerator Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 28

Why Consider DSP Alternatives § Wireless Systems requires more and more high performance and higher bandwidth DSP performance Performance 4 G/LTE Advanced ~10, 000 MIPS 1 Gbps – 500+ Mbps 3 G 2. 5 G 2 G might not be enough for future applications ~100, 000 MIPS 384 -3000 Kbps ~10, 000 MIPS 64 -384 Kbps ~100 MIPS 8 -13 Kbps Bit Rate Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 29

What are the alternatives § High-performance GPPs with DSP enhancements. Ø Ø Eliminating the need of a DSP and GPP for many products and thus reducing cost Example: Intel® Core™ Microarchitecture (i 3, i 5, i 7) ü ü ü § § § Two Single Instruction Multiple Data (SIMD) instructions allowing identical operations on multiple pieces of data in parallel. Intel Core instruction scheduler can issue four instructions simultaneously across five logical units: one Load and one Store unit, and three Arithmetic-Logical Units (ALUs) Intel® Advanced Vector Extensions (Intel® AVX) new three- and four operand (non-destructive) instructions, 256 -bit primitives for data permutes Multi-Core DSPs Application Specific Integrated Circuits (ASIC) Field Programmable Gate Array (FPGA) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 30

ASIC § Uses hard-wired logic with varied architectures according to the application (e. g. , 256 point hardware implemented FFT) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 31

ASIC - Advantages § § Speed Reduced Power Consumption Cost/performance Design Flexibility Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 32

ASIC- Disadvantage § § § Large development costs Lengthy development cycles Inflexibility Another Solution FPGA Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 33

What is FPGA § § § It is a network of reconfigurable hardware with reconfigurable interconnect controlled by a switching matrix Historically used for prototyping Recently includes DSP features Ø Major Companies DSP + FPGA: ALTERA (e. g. : Stratex) & XILINX (e. g. : Virtex II) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 34

FPGA - Advantages § § More Flexible than ASIC Huge Performance Gain in Some Applications Re-use hardware for different applications Highly parallel architectures Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 35

FPGA - Disadvantages § § Long Development Cycle Expensive compared to DSP Much higher chip-level power consumption compared to DSP Slow time to market compared to DSP Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 36

Why Still use DSP? § Several applications are not suited to be implemented in FPGA Ø Ø § Parallelism is sometimes inherently limited Speed is not always the highest factor to consider FPGA relatively expensive for terminal products (e. g. , cell phones) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 37

Why Still use DSP? § Comparison: DSP, FPGA, ASIC (ref: Bill Dally, Stanford University, IEEE ICASSP 04 Talk) DSP ASIC § < 10 MOPS/m. W § 50 -200 MOPS/m. W § ~0. 1 GOPS/$ § 2 -10 GOPS/$ § < 10 GOPS peak performance § Up to 1000 GOPS peak performance § 1 M $ programming cost § 10 M-15 M $ design cost § Programmable § Fixed FPGA § 2 -10 MOPS/m. W § ~1 GOPS/$ § Up to 500 GOPS peak performance § ~5 M $ design cost § Reconfigurable § New improved DSPs with more efficiency and parallelism (e. g. , multi-core) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 38

Types of DSP § Low End Fixed Point Ø § High End Fixed Point Ø Ø § TMS 320 C 55 XX, DSP 16 XXX, ADSP 215 XX, DSP 56800 Floating Point Ø § TMS 320 C 2 XX, ADSP 21 XX, DSP 56 XXX TMS 320 C 3 X, C 67 XX, ADSP 210 XX, DSP 96000, DSP 32 XX Berkeley Design Tech. Inc. Pocket Guide to DSPs http: //www. bdti. com/pocket. htm Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 39

Fixed Point Vs Floating Point § Fixed Point/Floating Point Ø fixed point processor are : ü ü cheaper smaller less power consuming Harder to program § ü ü Ø Limited dynamic range Used in 95% of consumer products floating point processors ü ü ü Ø Watch for errors: truncation, overflow, rounding have larger accuracy are much easier to program can access larger memory It is harder to create an efficient program in C on a fixed point processors than on floating point processors Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 40

What Chip will be used? § Freescale DSP 56858 Ø Ø Ø Family: DSP 56800 E Kit: DSP 56858 EVM Software: Metrowerks Code. Warrior ü Ø Applications ü ü § Metrowerks is a Freescale company in charge of developing the software Telephony Client side IP phone Internet Audio Voice Processing TI TMS 320 C 5510 Ø Ø Family: TMS 320 C 55 xx Kit: TMS 320 C 5510 DSK Software: TI Code Composer Studio Applications Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 41

Freescale/Motorola Family Tree Ref: Motorola DSP Selection Guide: http: //www. freescale. com/files/shared/doc/selector_guide/SG 1004. pdf Floating Point DSP Chips Discontinued!! Freescale DSP Family Tree [2003] TI Tree 56800 E DSP 56 F 801 DSP 56 F 802 DSP 56 F 803 DSP 56 F 805 DSP 56 F 807 DSP 56 F 826 DSP 56 F 827 DSP 56852 DSP 56853 DSP 56854 DSP 56855 DSP 56857 Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 56300 DSP 56301 DSP 56303 XC 56309 XC 56 L 307 DSP 56311 DSP 56321 DSPB 56362 DSPB 56364 DSPB 56366 DSPA 56367 DSPA 56371 DSP 56858 MC 56 F 8322 MC 56 F 8323 MC 56 F 8345 MC 56 F 8346 MC 56 F 8357 42 MSC 8100 MSC 8101 MSC 8103

56800 DSP Family, 16 -bit Fixed Point Specifications Features Applications • Processing capability of up to 35 million instructions per second (MIPS) § Single-instruction cycle 16 -bit x 16 -bit parallel multiply-accumulator • Running at 70 MHz • Two 36 -bit accumulators including extension bits • Requires only 2. 7– 3. 6 V of power • Single-instruction 16 -bit barrel shifter • Parallel instruction set with unique DSP addressing modes • Low-power wait and stop modes • Operating frequency down to DC • 16 -bit Timer Module • Motion Control ü Smart appliances ü Environmental controls ü Instrumentation • Industrial ü Uninterruptable power supplies ü Noise cancellation/suppression ü Temperature control • Synchronous serial interface module (SSI) ü HVAC • Serial peripheral interface (SPI) ü Inverters and AC-to-DC conversion • Programmable general-purpose I/O ü Lighting ü Automation • Transportation • Instrumentation Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 43

56800 E DSP Family, 16 -bit Fixed Point Specifications • Processing capability of up to 120 million instructions per second (MIPS) • Running at 120 MHz • Requires only 2. 7– 3. 6 V of power Features Applications § 40 K x 16 -bit Program SRAM § 24 K x 16 -bit Data SRAM ü Telco interface § 1 K x 16 -bit Boot ROM ü Codecs §Access up to 2 M words of program memory or 8 M data memory ü LCD and Keypad support §Six (6) independent channels of DMA Includes Also the MC 56 F 300 Series which contains on chip Flash memory §Two (2) Enhanced Synchronous Serial Interfaces (ESSI) §Two (2) Serial Communication Interfaces (SCI) §Serial Port Interface (SPI) § 8 -bit Parallel Host Interface §General Purpose 16 -bit Quad Timer §JTAG/Enhanced On-Chip Emulation (On. CE) for unobtrusive, real-time debugging §Computer Operating Properly (COP)/Watchdog Timer §Time-of-Day (TOD) §Up to 47 GPIO Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP • Telephony 44 • Client-side IP phone • Internet Audio ü Internet Audio decoding ü Internet Audio stand-alone player • Voice Processing

56300 DSP Family, 24 -bit Fixed Point Specifications • Processing capability of up to 480 million instructions per second (MIPS) • Running at 240 MHz • Requires only 1. 6– 3. 3 V of power Features Applications §Object code compatible with the DSP 56000 core with highly parallel instruction set §Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 x 24 -bit parallel Multiplier-Accumulator (MAC) §Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses §Digital Phase Lock Loop (DPLL) allows change of low-power Divide Factor (DF) without loss of lock §Hardware debugging support including On-Chip Emulation (On. CETM) module, Joint Test Action Group (JTAG) Test Access Port (TAP) §Two Enhanced Synchronous Serial Interfaces (ESSI 0 and ESSI 1 §Serial Communications Interface (SCI) §Triple timer module §Up to 34 GPIO Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 45 • Multimedia • Telecommunciation • Video conferencing • Base transceiver stations • Packet telephony

MSC 8100 Family, 16 -bit Fixed Point Specifications Features Applications • Processing capability of up to 4400 million instructions per second (MIPS) §Four 250/275 MHz Star. Core SC 140 DSP extended cores • Running at 300 MHz § 16 ALUs on a chip deliver up to 4000/4400 MMACS • Requires only 1. 6– 3. 3 V of power §Performance equivalent to a 1. 0/1. 1 GHz SC 140 Core Optimized for networking infrastructure applications §Industry's largest on-chip SRAM memory § 1436 KB of internal memory §Efficient multi-level memory hierarchy §Dual external industry-standard 60 xcompatible buses § 9. 6 Gbps peak bus throughput §Four independent Time-Division Multiplex (TDM) Interfaces § 400 Mbps peak serial data throughput § Accesses various external memories, including SDRAMs, SSRAMs, EPROMs, and Flash Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 46 • 2. 5 G Wireless System • 3 G Wireless System • IP Telephony • Compression • G. 7 xx speech coders

TI Family Tree TI DSP Family Tree [2003] Ref: TI DSP Selection Guide http: //focus. ti. com/lit/ml/ssdv 004 m. pdf C 2000 C 24 x F 2407, F 2406 F 2403, F 2402 F 2401, C 2406 Freescale Tree C 28 x C 3 x F 2810 F 2812 C 33 C 32 C 31 C 30 C 2404, C 2402 C 2401, F 243 F 241, C 242 F 240 C 54 x + RISC C 55 x C 5416 C 5410 C 5470 C 5409 C 5471 C 5510 C 5509 C 5502 C 5501 C 5407 C 5404 C 5402 C 5401 C 55 x + RISC C 62 x C 64 x C 67 x C 6211 C 6416 C 6713 C 6205 C 6415 C 6712 C 6204 C 6414 C 6711 C 6203 C 6412 C 6701 C 6202 C 6411 C 6201 DM 640 OMAP 5910 DM 641 C 549 DM 642 C 54 CST, C 54 V 90 Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP C 6000 C 5000 C 3000 47

TMS 320 C 24 x ™ DSP Generation, 16 -bit Fixed Point - Control Optimized DSP Specifications Features Applications • Up to 40 -MIPS operation • 375 -ns (minimum conversion • Appliances • Three power-down modes time) analog-to-digital (A/D) • Compressors • 3. 3 -V and 5 -V designs converter • Industrial automation • Dual 10 -bit A/D converters • Uninterruptible power (UPS) systems • Up to four 16 -bit general-purpose • Automotive braking steering systems timers • Watchdog timer module • Up to 16 PWM channels • Up to 41 GPIO pins • Printers and copiers • Hand-held power tools • Five external interrupts • Up to 32 K words on-chip • Electronic cooling Intelligent sensors sectored Flash • Tunable lasers • I/O Modules • Consumer goods § Controller Area Network (CAN) interface module • Serial communications inter -face(SCI) • Serial peripheral interface (SPI) • Boot ROM (LF 240 x and LF 240 x. A devices) Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP • Electric metering 48 • Fuel pumps • Industrial frequency Remote monitoring • ID tag readers

TMS 320 C 28 x ™ DSP Generation, 16 -bit Fixed Point – Control Optimized DSP Specifications Features Applications • 32 -bit fixed-point C 28 x™ DSP core • Ultra-fast 20– 40 ns service time • Lighting • 150 -MIPS operation to any interrupts • 1. 8 -volt core and 3. 3 -volt peripherals • 32 -/64 -bit saturation, single-cycle • Optical networking (ONET) read-modify-write instructions, and 64/32 and 32/32 modulus division • High-performance ADC • 32 × 32 single-cycle fixed-point MAC • Dual 16 × 16 single-cycle fixed-point MACs • On Chip flash memory • I/O modules: SPI, SCI, CAN Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 49 • Power supplies • Industrial automation • Consumer goods

TMS 320 C 3 x ™ DSP Generation, 32 –bit Floating Point – First Generation Specifications • Performance up to 150 MFLOPS Features Applications • Highly-efficient C language engine • Parallel multiply and arithmetic/logical operations on integer or floating-point numbers in a single cycle • Large address space: 16 Mwords • Eight extended-precision registers § 32 bit Floating point §Digital audio §Laser printers, copiers, scanners §Bar-code scanners §Videoconferencing • Fast memory management with onchip DMA §Industrial automation and robotics §Voice/facsimile §Servo and motor control Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 50

TMS 320 C 54 x ™ DSP Generation, 16 -bit Fixed Point – Power Efficient DSP Specifications Features Applications • 16 -bit fixed-point DSPs • Integrated Viterbi accelerator • Digital cellular communications • Power dissipation as low as 60 m. W for 100 MIPS • 40 -bit adder and two 40 -bit accumulators to support parallel instructions • Personal communications systems (PCS) • Single- and multi-core products delivering 30– 532 MIPS performance • 1. 2 -, 1. 8 -, 2. 5 -, 3. 3 - and 5 -V versions available • 6 -channel DMA controller per core • 40 -bit ALU with a dual 16 -bit configuration capability for dual onecycle operations • 17 × 17 multiplier allowing 16 -bit signed or unsigned Multiplication • Personal digital assistants • Digital cordless communications • Wireless data communications • Four internal buses and dual address generators enable multiple program and data fetches and reduce memory bottleneck • Networking • Single-cycle normalization and exponential encoding • Portable Internet audio • Eight auxiliary registers and a software stack enable advanced fixed -point DSP C compiler • Power-down modes for battery powered applications Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP • Pagers 51 • Computer telephony • Voice over packet • Modems

TMS 320 C 54 x ™ DSP + RISC, 16 -bit Fixed Point – System Level DSP Specifications • Dual CPU processor integrating a TMS 320 C 54 x™ DSP core and an ARM 7 TDMI™ RISC • 1. 8 -volt core and 3. 3 -volt peripherals Features Applications TMS 320 C 54 x DSP core subsystem • wireless data • 100 -MIPS operation • Smart pen pads • 72 kwords RAM • Two multi-channel buffered serial ports (Mc. BSPs) • Voice recognition • Direct memory access (DMA) controller • Vommand control • Phase-locked loop • Access point controller • External memory interface • Networked security • ARM port interface (API) • Industrial control and emergency ARM 7 TDMI RISC core subsystem radio • 47. 5 -MHz operation • 16 KByte zero-wait-state SRAM • Memory interface (SDRAM, SRAM, ROM, Flash) • Single-port 10/100 Base-T Ethernet Interface (C 5471 DSP only) • 36 general-purpose I/O (ARMI/O) • Two UARTs (one Ir. DA) • Serial peripheral interface (SPI) • I 2 C interface Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP • Text-to-speech 52

TMS 320 C 55 x ™ DSP Generation, 16 -bit Fixed Point – Most Power Efficient DSP Specifications Features Applications • C 55 x™ DSP core delivers 300 MHz for up to 600 -MIPS performance • Advanced automatic power management • Feature-rich, miniaturized per- • 1. 6 -volt core and 3. 3 -volt peripherals • Configurable idle domains to extend your battery life • 2 G, 2. 5 G and 3 G cell phones sonal and portable products • Shortened debug for faster time-tomarket and basestations • 144 -MHz/200 -MHz clock rate • Digital still cameras • 256 -KB RAM, 64 -KB ROM • Electronic books • Three Mc. BSPs, I 2 C, watchdog • Voice recognition timer, general-purpose timers • GPS receivers • USB 2. 0 full-speed (12 Mbps) • Fingerprint/Pattern recognition • 10 -bit ADC • Wireless modems • real-time clock (RTC) • Headsets • Digital audio players • Biometrics Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 53

TMS 320 C 55 x ™ DSP + RISC, 16 -bit Fixed Point – OMAP Processor Specifications • Dual CPU processor integrating a TMS 320 C 55 x™ DSP core and an ARM 925 TDMI™ RISC @150 MHz • 1. 8 -volt core and 1. 8 -volt peripherals Features Applications § 150 -MHz TI-enhanced ARM 925 • 16 KB instruction cache and 8 KB data cache • Applications processing • Data and instruction MMUs • Enhanced gaming • 32 -bit and 16 -bit instruction sets • Webpad 150 -MHz TMS 320 C 55 x™ DSP • Point-of-sale • 12 KW (24 KB) instruction cache • Medical devices • 80 KW (160 KB) SRAM • Industry-specific PDAs • 16 KW (32 KB) ROM • Telematics • Two 16 -bit memory interfaces • Digital media processing for SDRAM and flash • Military and government cellular • Nine-channel system DMA controller • LCD controller • USB 1. 1 host and client • MMC/SD card interface • Seven serial ports plus three UARTs, Nine timers, Keyboard interface • Less than 250 m. W at 1. 6 V Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP • Internet appliances 54

TMS 320 C 62 x ™ DSP Generation, 16 -bit Fixed Point – High Performance DSP Specifications • 16 -bit fixed-point DSPs • Up to 2400 MIPS • Running at 300 Mhz Features Applications • C 6000™ DSP Platform Veloci. TI™ advanced architecture • Pooled modems • Up to eight 32 -bit instructions executed each cycle • Wireless basestations • Eight independent, multi-purpose functional units thirty-two 32 -bit registers • Industry’s most advanced C compiler and Assembly Optimizer maximize efficiency and performance • Digital Subscriber Line (x. DSL) • Central office switches • Private Branch Exchange (PBX) • Digital imaging • Call processing • 3 D graphics • Speech recognition • Voice over packet Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 55

TMS 320 C 67 x ™ DSP Generation, 32 -bit Floating Point – High Performance DSP Specifications • 32 -bit loating point DSPs • Up to 1350 MFLOPS • Running at 225 Mhz Features Applications • C 6000™ DSP Platform Veloci. TI™ advanced architecture • Pooled modems • Up to eight 32 -bit instructions executed each cycle • Wireless basestations • Eight independent, multi-purpose functional units thirty-two 32 -bit registers • Industry’s most advanced C compiler and Assembly Optimizer maximize efficiency and performance • Central office switches • Private Branch Exchange (PBX) • Digital imaging • Call processing • 3 D graphics • IEEE floating-point format • Speech recognition • Up to 1350 MFLOPS at 225 • Voice over packet • Two new multi-channel serial ports (Mc. ASP) (C 6713 DSP) can support up to stereo channels of I 2 S (Inter IC Sound) and compatible with S/PDIF transmit protocol. Note I 2 S is a protocol for transmitting 2 channels of digital audio over a single serial connection Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP • Digital Subscriber Line (x. DSL) 56

TMS 320 C 64 x ™ DSP Generation, 16 -bit Fixed Point – High Performance DSP Specifications • 16 -bit fixed point processor TMS 320 C 64 x DSP high performance core provides scalable performance of up to 1. 1 GHz • The industry’s fastest DSPs with up to 600 MHz (4800 MIPS) performance • C 64 x DSPs are software compatible with TI’s C 62 x™ DSPs Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP Features Applications • C 6000™ DSP Platform Veloci. TI™ advanced architecture • DSL and pooled modems • Up to eight 32 -bit instructions executed each cycle • Wireless LAN • Eight independent, multi-purpose functional units thirty-two 32 -bit registers • Industry’s most advanced C compiler and Assembly Optimizer maximize efficiency and performance • Basestation transceivers • Enterprise PBX • Multimedia gateway • Broadband video transcoders • Streaming video servers and clients • Highspeed raster image processing (RIP) 57

TI Families Summary § § § § C 24 x and C 28 x families: low performance 16 -bit fixed point used for control purpose C 54 x family: mid-range performance 16 -bit fixed point C 55 x family: mid-range performance 16 -bit fixed point with reduced power consumption and increased parallelism C 5000 + RISC microprocessor: used for embedded applications such as cell phone and PDAs C 62 x: high-range performance 16 -bit fixed point supporting VLIW architecture C 64 x: very high performance 16 -bit fixed point with extension capabilities of C 62 x with higher clock frequency (>2500 MIPS) C 3 x: first generation low performance 32 -bit floating point C 67 xx family: very high performance 32 -bit floating point Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 58

Very Large Instruction Width (VLIW) § VLIW architectures execute multiple instructions/cycle and use simple, regular instruction sets Ø Ø § § § More parallelism, higher performance Better compiler target Multiple independent instructions per cycle, packed into single large "instruction word" or "packet“ Large, uniform register sets Wide program and data buses Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 59

VLIW – Simplified Architecture Example Program Memory 256 bits consisting of 8 instructions Each instruction is 32 bits Execution Units Execution Units Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 60 Each unit executing one instruction

DSP Processor Selection Criteria § § Wide range of DSP processors are available, which one to select? It depends about the application: what is the most important criteria? Ø Ø Ø Ø Speed. Memory bandwidth. Cost. Ease of use of development tools. Packaging options. On-chip integration. Power consumption. Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 61

DSP Processor Selection Criteria § Use of available benchmarks: Ø Ø § BDTI kernel benchmarks. BDTI application benchmarks. Use a hierarchical approach to pick a processor Ø Ø Ø List your requirements. Start with critical criteria; and prioritize the remaining ones. Trade-offs may be required. Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 62

Software Coding § § § Proptotype in a scripting language (Matlab, Python) to validate Write Code in C Compile to create Assembly code Assemble the code to create object code and link Use simulator to test the speed of the code If code is not fast enough - rewrite the C code and test again. If not fast enough yet, write in Assembly language Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 63

Why use Assembly? § Most C compilers for DSP chips produce code that does not fully utilize the capabilities of the DSP Ø Ø § § Data Fetch parallel to execution Parallel execution The C code can be 3 to 30 times slower than the best assembly code possible. Especially in the signal processing parts of the code. The problem is more acute with fixed-point DSPs Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 64

But I don't want to write Assembly § Have somebody else write assembly for you Ø § § use libraries Rewrite your C code to produce a better assembly code Test and profile your code to see which parts of the software take most of the CPU time. Limit Assembly code to subroutines: Ø Ø That the program spends a lot of time in them That benefit from the special functions of DSP such as MACS and parallel execution and fetch. Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 65

How to Write a Better C Code § § Use Simple Loops Avoid if statements in loops Avoid subroutine calls statements in loops Use inline subroutines Ø Ø Ø § § § Compiler inserts function directly into the caller's code stream (conceptually similar to what happens with a #define macro) Avoids the subroutine call over head (saving volatile variables) Increases code size Avoid division and modulo operations Use and (&) and shift when possible Use 5%/80% rule Ø Ø Program in Assembly the 5% of the lines of code of the project that take 80% of the CPU load. Try to change your code to fit existing assembly routines. Ira A. Fulton Schools of Engineering School of ECEE EEE 404/591 – Real-Time DSP 66