Dynamically Reconfigurable Architectures An Overview Juanjo Noguera Dept

Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC) jnoguera@ac. upc. es

Outline n Introduction n Reconfigurable Computing • Reconfigurable devices and systems • Reconfigurable Systems Classification • Reconfiguration Methods n Reconfigurable Instruction Set Processors • ASIP-based approach • Coprocessor-based approach n Conclusions 2

Introduction n Reconfigurable Computing (RC) is an emerging paradigm for digital systems design n Technology improvements have made possible new programmable logic devices (FPGAs, CPLDs) n Objective of the talk: Give an overview of RC concepts and introduce the Reconfigurable Instruction Set Processors. 3

Introduction (II) n RC objectives: Specialization, performance, flexibility l l Performance Power consumption Specialization l l Flexibility Programming n Basic idea: “Programmable Hardware” 4

Introduction (III) n RC comparison versus other alternatives Flexibility, Power Performance Application Specific Systems GPP Reconfigurable Computing DSP General Purpose Systems RC ASIC Performance Cost 5

Outline n Introduction n Reconfigurable Computing • Reconfigurable devices and systems • Reconfigurable Systems Classification • Reconfiguration Methods n Reconfigurable Instruction Set Processors • ASIP-based approach • Coprocessor-based approach n Conclusions 6

Reconfigurable Computing Reconfigurable Devices n General device architecture I/O Bloc Logic Bloc Interconnection Structure 7

Reconfigurable Computing Reconfigurable Devices (II) n Routing strategies A B C Continuous Routing A B C Structured Routing 8

Reconfigurable Computing Reconfigurable Devices (III) n SRAM based devices with infinite number of reconfigurations Configuration Bitstream 110011101. . . • App 1 -> Bitstream 1 • App 2 -> Bitstream 2 • App n -> Bitstream n Reconfigurable Device 9

Reconfigurable Computing Reconfigurable Systems (I) n Rapid System (ASIC) Prototyping CPU PLD PLD PLD 10

Reconfigurable Systems (II) Reconfigurable Computing n Reconfigurable Systems Classification Host Computer (d) PLD (c) CPU RAM PLD SYSTEM BUS (b) PLD RAM I/O PLD RAM (a) 11

Reconfigurable Computing Reconfiguration Methods (I) n Compile Time Reconfiguration (CTR) • Device configuration is fixed during application run time execution n Run Time Reconfiguration (RTR) • Device configuration changes during application run time execution n RTR strategies • Global RTR • Partial RTR 12

Reconfigurable Computing Reconfiguration Methods (II) n Global Run Time Reconfiguration (Single context) Application #1 Reconfiguration Execution #2 Reconfiguration #2 #1 #4 #3 #4 Reconfiguration Contexts Dynamically Reconfigurable Device 13

Reconfigurable Computing Reconfiguration Methods (III) n Partial Run Time Reconfiguration (Multiple context) Aplicació #1 Reconfiguration #2 #3 #4 #1 #3 #2 #4 Reconfiguration Contexts Dynamically Reconfigurable Device 14

Reconfigurable Computing Reconfiguration Methods (IV) n Run-Time Reconfiguration Challenges • Temporal Partitioning • Context Scheduling (static) n Reconfiguration Latency Overhead • Configuration Pre-fetching • Configuration Caching • Configuration Compression 15

Outline n Introduction n Reconfigurable Computing • Reconfigurable devices and systems • Reconfigurable Systems Classification • Reconfiguration Methods n Reconfigurable Instruction Set Processors • ASIP-based approach • Coprocessor-based approach n Conclusions 16

Reconfigurable Instruction Set Processors Introduction n By including reconfigurability we can increase flexibility with high specialization Processor PLD Reconfigurable Processor 17

Reconfigurable Instruction Set Processors Introduction (II) n Coprocessor based approach ··· Task 1 ··· Task K+1 Task K Software Task N Hardware n ASIP based approach · · · Software Hardware Task 1 Task 2 Task N 18

Reconfigurable Instruction Set Processors Coprocessor based approach (I) n Typical example: CPU + PCI board • Altera ARC-PCI • Compaq Pamette n System on Chip (So. C) • Altera´s Excalibur device • Chameleon Systems, Inc. 19

Reconfigurable Instruction Set Processors Coprocessor based approach (II) n Altera ARC-PCI 20

Reconfigurable Instruction Set Processors Coprocessor based approach (III) n Compaq Pamette 21

Reconfigurable Instruction Set Processors Coprocessor based approach (IV) n Altera´s Excalibur device • Embedded Processor: ARM, MIPS or NIOS 22

Reconfigurable Instruction Set Processors Coprocessor based approach (V) n Chameleon Systems, Inc. 23

Reconfigurable Instruction Set Processors ASIP based approach (I) n Reconfigurable unit within CPU Fetch Decode Issue Integer Unit FP Unit Branch Unit LD/ST Unit Reconfigurable Unit 24

Reconfigurable Instruction Set Processors ASIP based approach (II) n Challenge: CAD tools C Code Compiler Instruction Description Assembly Code (Configuration bits) 25

Reconfigurable Instruction Set Processors ASIP based approach (III) C Code Compiler Structure C Parsing Optimizations Inst. Identification Hardware Estimator Inst. Selection Config. Scheduling Hardware Generation Code Generation Assembly Code Configuration bits 26

n Example: Philips Cin. CISe Architecture 5 32 32 MUX 5 Register File ALU 5 32 32 32 4 RFU Encoded Instruction Word Reconfigurable Instruction Set Processors ASIP based approach (II) 32 27

Reconfigurable Instruction Set Processors ASIP based approach (III) n Application example: DES & A 5 encryptation algorithms 27 26 25 23 22 30 27 26 25 7 6 5 4 3 2 srl andi or sll $13, $2, 20 $25, $13, 1 $14, $2, 21 $24, $14, 6 $15, $24 $13, $2, 22 $14, $13, 56 $25, $14 $24, $25, 2 22 XOR srl xor andi $24, $5, 18 $25, $5, 17 $8, $24, $25 $9, $5, 16 $10, $8, $9 $11, $5, 13 $12, $10, $11 $13, $12, 1 28

Conclusions n Reconfigurable Computing is an emerging and interesting computing paradigm n RC devices and architectures are becoming a reality n There is a big challenge is High-level synthesis (CAD) tools 29

Conclusions (II) n What is the future ? ? Flexibility, Power ? ? RC GPP DSP RC RC ASIC Performance 30