Modeling Dynamically Reconfigurable Systems via RewritingLogic modeling and
Modeling Dynamically Reconfigurable Systems via Rewriting-Logic (modeling and simulation of the FFT in Optimal Space) C. Llanos 2, 4 , M. Ayala-Rincón 1, 4, R. B. Nogueira 2, 4, R. P. Jacobi 3, 4 R. W. Hartenstein 5, 6 1 Departamentos and de Matemática, 2 Engenharia Mecânica e 3 Ciência da Computação Universidade de Brasília Informatik, 6 Kaiserslautern University of Technology 4 5 Fachbereich 2 nd Dagsthul Seminar on Dynamically Reconfigurable Architectures Dagsthul, Germany, July 20 -25, 2003 Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 1
Overview(Arvind aproach) Ø Applying rewriting techniques in hardware design [Arvind et al] • • specification of correct processors Cache protocols over memory systems Specification of digital circuits Specification and verification of network protocols Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 2
Characteristic of Arvind’s approach Ørewriting is neither applied for simulation nor for verification ØProposal Translate to Verilog! Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 3
Overview (using Haskell) • Bejesse et al use Haskell (a functional language) for circuit design, specification and verification • These ideas are implemented in LAVA system • This approach shows how the high level abstraction of functional languages is suitable for hardware design Lava approach takes advantage of high level abstraction provided by functional languages Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 4
Overview (Kapur Approach) ØKapur has used his well-known Rewriting Rule Laboratory - RRL for verifying arithmetic circuits ØRRL is used to verify automatically properties of arithmetic hardware circuits (adders, multipliers, SRT division circuits) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 5
Why Rewriting? ØRewriting is the formal framework of all functional languages ØThis fact allows us to work in more abstract levels ØRewriting assistant environments help in the task of formal verification of hardware Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 6
Rewriting Rules right side left side l r if C Premise to be hold Rewriting Rule Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 7
Rewriting Ø Rewriting rules: l r if C Premise to be hold Semantic: “l is replaced by r if C is true” Ø Operational semantics: a rule is applied to a term, when its left-side matches a sub-term, replacing the matched subterm with the corresponding right-side of the rule. All that, whenever the premise C of the rule holds. Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 8
Specifying Processors (Arvind’s proposal) SYS(mem, Proc) Data Mem +1 PC Int Mem Register File ALU PROC(ia, rf, prog) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 9
Specifying Processors • Basic Processor – Single cycle, non pipelined, in-order execution • SYS : = Sys(MEM, PROC) • PROC : = Proc(ia, rf, prog) • AX Architecture Instruction set: r: =Loadc(v) r: =Op(r 1, r 2) r: =Load(r 1) r: =Loadpc Jz(r 1, r 2) Store(r 1, r 2) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 10
Defining Instruction of the processor by rewriting rules Jz-jump-rule: Conditional jump [Jz(r 1, r 2)] Proc(ia, rf, prog) Proc(rf[r 2], rf, prog) if im[ia] = jz(r 1, r 2) and rf[r 1] = 0 Rewriting rules can implement state transitions in the processor Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 11
Example: Euclid’s Algorithm for greatest common divisor (GCD) GCD Mod Rule Gcd(a, b) Gcd(a-b, b) if (a b) (b 0) GCD Flip Rule Gcd(a, b) Gcd (b, a) if a < b v. The term Gcd(6, 15) can be reduced by applying the Mod and Flip rules Gcd(6, 15) Flip Gcd (6, 3) Gcd(15, 6) Mod Gcd(3, 3) Gcd (9, 6) Mod Gcd(3, 0) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems Result! 12
Characteristic of Rewriting ØRules are applied non-deterministically ØControlling the execution of rules can be accomplished by logic Rewriting-Logic = Rewriting Rules + Strategies Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 13
Examples of Rewriting Oriented Environments ØELAN: it has great flexibility for defining types and ease manipulation of strategies ØMaude: • It’s necessary to do more effort for description • it provides model checking useful for hardware verification Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 14
Example of a Reconfigurable Architecture functional Units R 2 Op 2 R 1 C 1 Ar 1 Constant Register Ar 2 Op 1 Address register P 1 P 2 Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems Address register 15
Example of Reconfigurable Architecture R 2 Op 2 * R 1 C 1 At some time the configuration can be specified 011 100 Ar 1 Ar 2 AND 1 100 Op 1 P 2 Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 16
Describing Architectures in ELAN R 2 * Op 2 R 1 C 1 011 100 Ar 1 AND 1 Op 1 P 1 const(@) port(@) reg(@) addr(@) @, @, @ [ @ # @ ] Ar 2 100 Problem: how can this architecture be described in ELAN Using and defining types It’s possible to describe fixed parts and reconfigurable ones P 2 : : : : ( ( ( ( complex. Unit ) Const; complex. Unit ) Port; complex. Unit ) Reg; int ) Addr; int Port Reg ) fix. MAC; Addr Const Op. Unit ) rec. MAC; fix. MAC rec. MAC ) MAC; Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 17
Describing more Complex Architectures R 2 Op 2 R 1 C 1 Ar 2 Op 1 P 1 R 2 Op 2 R 1 C 1 Ar 2 Op 1 P 2 Processor @, @, @ [ @ # @ ] < @ @ @ @ @ MAC )Proc; > : ( int Port Reg ) fix. MAC; : ( Addr Const Op. Unit ) rec. MAC; : ( fix. MAC rec. MAC ) MAC; : ( int r. Array. Struct MAC MAC Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 18
How the Execution Process is described in the ELAN system < [0, port(c. Port 1), port(c. Port 2), reg(c. Reg 1), reg(c. Reg 2)# addr 1, addr 2, const(c. Const 1), op 1, op 2] > < [0, port(c. Port 1), port(c. Port 2), reg(c. Reg. Res 1), reg(c. Reg. Res 2) # addr 1, addr 2, const(c. Const 1), op 1, op 2] > where c. Reg. Res 1 : =() operate(c. Port 1, c. Port 2, op 1) where c. Reg. Res 2 : =() operate(c. Reg 1, c. Const 1, op 2) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 19
How the Reconfiguration Process is described in ELAN system [] reconfigure(MACs. Array( [ fix 0 # rec 0 ] ) MACs. Array([ fix 0 # get. Rec. MAC(MAConfig 0) ] ) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 20
Using Strategies in ELAN strategies for Proc implicit [] process input; repeat*(reconfiguration; propag ation; execution); output end ØUsing strategies for guiding the application of the rules ØStrategies in ELAN allow to separate execution and reconfiguration steps ØThis approach allows a closer specification to transference register description (RTL Description) Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 21
Reconfiguration for FFT a 0 b 0 a 4 b 1 a 2 b 2 a 6 b 3 a 1 b 4 a 5 b 5 a 3 b 6 a 7 b 7 Number of reconfiguration = ln(n) + 1 Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 22
FFT in Optimal Space 0 MAC 0 1 MAC 1 2 3 MAC 2 MAC 3 4 5 MAC 4 6 MAC 5 MAC 6 7 MAC 7 Interconnections in reconfiguration step 3 Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 23
An Execution Rule for a pair of MACs [MAC 01] < [0, port(c. Port 1), port(c. Port 2), reg(c. Reg 1), reg(c. Reg 2)# addr 1, addr 2, const(c. Const 1), op 1, op 2] [1, port(c. Port 3), port(c. Port 4), reg(c. Reg 3), reg(c. Reg 4)# addr 3, addr 4, const(c. Const 2), op 3, op 4] < > [0, port(c. Port 1), port(c. Port 2), reg(c. Reg. Res 1), reg(c. Reg. Res 2) # addr 1, addr 2, const(c. Const 1), op 1, op 2] [1, port(c. Port 3), port(c. Port 4), reg(c. Reg. Res 3), reg(c. Reg. Res 4) # addr 3, addr 4, const(c. Const 2), op 3, op 4] > where c. Reg. Res 1 : = () operate( c. Port 1, c. Port 2, op 1 ) where c. Reg. Res 2 : = () operate( c. Reg. Res 1, c. Const 1, op 2 ) where c. Reg. Res 3 : = () operate( c. Port 3, c. Port 4, op 3 ) nd Modeling DRS via Rewriting-Logic, 2 Dagstuhl Seminar on Dynamically Reconfigurable Systems 24
A Reconfiguration Rule for a pair of MACs [reconfiguration] < [ fix 0 # rec 0 ] [ fix 1 # rec 1 ] > < [ fix 0 # addr(0), addr(2), const( < 1, 0000 0, 0000 > ), < + >, < * > ] [ fix 1 # addr(1), addr(3), const( < 1, 0000 0, 0000 > ), < + >, < * > ] > Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 25
A Pipelined Reconfigurable FFT (eliminating the reconfiguration overhead) Reconfigurable Interconnection Network ØWhile one Mac array is being reconfigured the other array is computing one step of FFT Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 26
Advantages of ELAN Environment ØELAN has the advantage of an embedded inference engine v a flexible type definition mechanism (data and operators) v a powerful manipulation of typed expressions through rules and meta-rules v the availability of logical strategies to control their application. Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 27
Conclusions ØThe high abstraction of Rewriting Environments makes design exploration easier ØUsing ELAN is possible to simulate the description of the architecture ØDescriptions in ELAN are close to the physical architecture Modeling DRS via Rewriting-Logic, 2 nd Dagstuhl Seminar on Dynamically Reconfigurable Systems 28
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