Digital Electronics Technology Sachin Sharma Counters ASYNCHRONOUS COUNTERS

Digital Electronics Technology Sachin Sharma Counters

ASYNCHRONOUS COUNTERS • Only LSB flip-flop controlled by the clock input • Also known as a RIPPLE COUNTER • Two or more “T” flip-flops interconnected, output of each flip-flop connected to clock input of the next. • Modulus- number of stable states in each flip-flop cycle • Modulus = N= number of flip-flops • Highest number in count =

BUILD A 4 BIT RIPPLE COUNTER 1. 4 JK flip-flops in toggle mode- all JK inputs tied high 2. Q outputs connected to clock input of following flip-flop 3. FF A = LSB (one with clock input); toggles when input clock toggles from high to low; FF D = MSB 4. FF B, C, D do not toggle till receive NGT from proceeding FF 5. Direction of count can be reversed by complementing each FF’s output or complementing each FF’s input

TEST 1. What is the term for the number of counts in one counter cycle? Modulus of the counter 2. How is the modulus determined? 3. Since only the first flip-flop of a ripple counter is controlled by a clock, the counter is __________? Asynchronous 4. What is the mod number of a counter containing 5 flip-flops? 32 5. What is the highest count of a four bit counter? 31

PROGRAMMING A RIPPLE COUNTER • Counters may be made to recycle after any desired count by using a gate to reset the counter. CONVERT MOD 8 TO MOD 6 UNSTABLE STATE

HOW TO BUILD A COUNTER TO GO FROM ZERO TO MOD NUMBER X 1. Determine smallest number of FF’s such that 2. Connect a NAND gate output to asynchronous clears of all FF’s 3. Determine which FF’s will be high at count = X Connect the Q outputs of these FF’s to NAND gate inputs

BUILD A COUNTER THAT COUNTS FROM ZERO TO NINE (X=MOD 10) 1. Determine smallest number of FF’s such that thus 4 FF’s are required 2. Connect a NAND gate to asynchronous clears of all FF’s 3. Determine which FF’s will be high at count = X Connect the Q outputs of these FF’s to NAND gate inputs 1 1 0 0

PROGRAMMING COUNTERS USING JK INPUTS • Counters can be controlled using the JK inputs • Low on JK of 1 st FF will cause it to stop toggling on any count • High or low at JK inputs forces counter to skip states

ASYNCHRONOUS DOWN COUNTER • Direction of count can be reversed by (a) complementing each FF’s output or (b) complementing each FF’s input

COUNTER PROBLEM 1. What is the value of the last usable state before the NAND gate resets the circuitry? 2. What value does the NAND gate reset the value to? 3. What is the modulus of this counter? 4. If count starts at decimal 11 and receives seven clock pulses, what is the new value on the counter? 5. What is the unstable state of the counter?

COUNTER PROBLEM 1. What is the value of the unstable state, in decimal? 2. At what value does the NAND gate set the counter to? 3. If QA=1, QB=1, and QC=0, and 5 clock pulses are applied: QC= QB= QA= 4. What is the modulus of this counter?

BCD COUNTER • Binary counter that counts from 0000 to 1001 before it recycles (MOD-10). • Widespread applications where pulses or events are to be counted and the results displayed on a decimal numerical read-out. • Also used for dividing a pulse frequency exactly by 10. Cascading BCD counters to count and display from 000 to 999.

MOD-60 COUNTER Two 7493 s can be combined to produce a MOD-60 Counter

DIGITAL CLOCK

COUNTERS ASYNCHRONOUS

SYNCHRONOUS COUNTERS • Two or more FF’s connected as “T” FF’s. • All FF’s in the counter are clocked at the same time. • Advantage over the ripple counter is speed and accuracy but more complex.

SYNCHRONOUS COUNTERS N MOD <2 • A NAND control gate is used to clear the counter before the full count.

SYNCHRONOUS COUNTERS UP/DOWN

COUNTER TYPES Asynchronous Counter (a. k. a. Ripple or Serial Counter): each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain. Synchronous Counter (a. k. a. Parallel Counter): all the FF’s in the counter are clocked at the same time. Up Counter: counter counts from zero to a maximum count. Down Counter: counter counts from a maximum count down to zero. BCD Counter: counter counts from 0000 to 1001 before it recycles. Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF. Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF.

RING COUNTER Shift register counter with feedback from Q of last FF back to first FF input

JOHNSON COUNTER Shift register in which the inverted output of the last FF is fed back to the input of the first FF.

Lab 18. A PROGRAMMABLE COUNTER Design a four-bit counter controlled by two control lines X and Y that behaves according to the truth table.

Lab 18. A PROGRAMMABLE COUNTER

RIPPLE COUNTER Binary Output Clock Input 00 1 10 10 1 Pulse 8 1 2 3 4 5 6 7 PS CLR input All 16 J-K flip-flops This Onand the 4 -bit next counter clockhas pulse (8) states all FFs and are in the will count toggle from because binary each 0000 will through receive 1111 INACTIVE TOGGLE MODE a H-to-L and then pulsereset one back after to another. 0000. Watch Thethe counter counthas ripple a modulus thru theof counter. 16.

RIPPLE COUNTER WITH WAVEFORMS Binary Output Clock Input 01 00 10 1 Pulse 5 1 2 3 4 Clock input FFs triggered on 1 s output H-to-L pulse. CLK toggles 1 s FF toggles 2 s FF. 2 s output 2 s FF toggles 4 s FF. 4 s output

DECADE COUNTER Binary Output Clock Input 111 ial c t i n I t 0 nt a ou 11 0 00 11 0 Pulse 8 1 2 3 4 5 6 7 Short negative pulse To clear input of each FF All J & K inputs = 1 All PR inputs = 1 To change mod-16 counter to decade counter: Count is at 1001. Reset count to 0000 after 1001 (9) count. Next clock pulse will increment counter for a When count hits 1010 reset to 0000. short time to 1010 which will activate the NAND gate See added 2 -input NAND gate that clears all and reset the counter to 0000. JK FFs to 0 when count hits 1010.

DOWN COUNTER 11 0 00 1 4 2 1 Pulse 5 3 Changes from Ripple Up Counter are wiring from Q’ outputs (instead of Q outputs) to the CLK input of the next FF. t oun c l a i Init t at se 111 y r a bin

SELF-STOPPING DOWN COUNTER 10 0 10 1 unt on tch coremained The Wacount. Pulse 8000. at binary 2 3 4 Pulse 8 1 5 6 7 This is a 3 -bit down counter. The 1 s FF is in TOGGLE mode when counting (J & K = 1). The 1 s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate when the count decrements to 000. The count stops at 000.

COUNTER USED FOR FREQUENCY DIVISION 8 100 Hz 50 Hz 16 Clock Input 800 Hz 200 Hz 4 400 Hz 2

USING THE 7493 COUNTER IC • Counters are available in IC form. • Either ripple (7493 IC) or synchronous (74192 IC) counters are available. 100 ? Hz Hz 400 ? Hz Hz ? Hz 800 Hz 1600 Hz 7493 Counter IC wired as a 4 -bit binary counter

MAGNITUDE COMPARATOR A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B). A(0) A(1) Inputbinary 0111 1111 0001 A(2) 74 HC 85 Magnitude Comparator A(3) B(0) B(1) Input binary 0110 0111 1100 B(2) B(3) A>B HIGH A=B HIGH A<B HIGH

TROUBLESHOOTING EQUIPMENT • • Logic Probe Logic Pulser Logic Clip (logic monitor) Digital IC Tester DMM/Logic Probe DMM or VOM Dual-trace Oscilloscope Logic Analyzer

SIMPLE TROUBLESHOOTING HINTS • Feel top of IC to determine if it is hot • Look for broken connections, signs of excessive heat • Smell for overheating • Check power source • Trace path of logic through circuit • Know the normal operation of the circuit