Data Converters EECT 7327 SampleandHold Fall 2014 Professor

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Sample-and-Hold (S/H) Basics – 1–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu ZOH vs. Track-and-Hold (T/H) • Zero acquisition time • Infinite bandwidth • Not realistic • T/2 acquisition time • Finite bandwidth • Practical – 2–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu A Simple T/H (Top-Plate Sampling) • MOS technology is naturally suitable for implementing T/H • The lowpass SC network determines the tracking bandwidth • Non-idealities: signal-dependent Ron, charge injection, aperture, etc. – 3–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Tracking Bandwidth (TBW) • Tracking bandwidth determines how promptly Vo can follow Vi • Typically TBW is many times greater than the max signal bandwidth • What’s wrong with the concept of “linear filtering” if Ron is constant? – 4–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Dispersion – 5– • Magnitude response • Non-uniform phase delay • Non-uniform group delay

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Dispersion • Waveform is not very sensitive to the lowpass magnitude response as long as the signal bandwidth is on the order of TBW • Waveform distortion is mainly due to non-uniform phase and group delays – 6–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Signal-Dependent Ron • Signal-dependent Ron → signal-dependent TBW → extra waveform distortion • Neither signal-dependent Ron nor dispersion is of concern if TBW is sufficiently large (>> fin, depending on the target accuracy) – 7–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Ideal T/H • Sufficient tracking bandwidth → negligible tracking error • Well-defined sampling instant (asserted by clock rising/falling edge) • Zero track-mode and hold-mode offset errors – 8–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu T/H Errors (Track Mode) • Finite tracking bandwidth → tracking error, T/H memory • Track-mode offset, gain error, and nonlinearity – 9–

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Acquisition Time (tacq) Accuracy tacq 1% (7 b) ≥ 5 t 0. 1% (10 b) ≥ 7 t 0. 01% (13 b) ≥ 9 t Short L, thin tox, large W, large Vov, and small Vi help reduce Ron – 10 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu T/H Errors (T-to-H Transition) • Pedestal error (often signal-dependent) resulted from switch turn-off nonidealities (clock feedthrough and charge injection) • Aperture delay – the delay Δt b/t hold command hold action • Aperture jitter – the random variation in Δt (i. e. , sampling clock jitter) – 11 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Switch Non-Idealities Clock feedthrough (CF) Fast turn-off Slow turn-off – 12 – Charge injection (CI)

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Pedestal Error of Top-Plate T/H Slow turn-off: Fast turn-off: Watch out for nonlinear errors! – 13 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Speed-Accuracy Tradeoff of T/H Pedestal error: TBW: Therefore: Technology scaling improves T/H performance! – 14 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Aperture Delay (Δt) • Fixed aperture delay is usually not of problem in a single-path T/H • Non-uniform aperture delays among time-interleaved T/H paths cause significant errors (Δt 1, Δt 2… are also called sampling clock skew) – 15 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Aperture Jitter Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed sampling systems, ” IEEE Journal of Solid-State Circuits, vol. 25, issue 1, pp. 220224, 1990. – 16 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Aperture Jitter – 17 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Aperture Jitter – 18 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu T/H Errors (Hold Mode) • Hold-mode droop caused by off-switch/diode/gate leakage • Hold-mode input feedthrough (i. e. , due to capacitive coupling) – 19 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Evaluating T/H Performance k. T/C noise: T = 300 K SNDR: Noise Distortion Jitter – 20 – CS √k. T/C 100 p. F 6. 4μV 1 p. F 64μV 10 f. F 640μV

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu MOS S/H Techniques – 21 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Simple Top-Plate Sampling Pros • Simple, minimum number of devices • Potentially wideband, zero track-mode offset Cons • Signal-dependent tracking bandwidth • Signal-dependent charge injection and clock feedthrough • Signal-dependent aperture delay (sampling point) – 22 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Signal-Dependent Aperture Delay • Non-uniform sampling due to signal-dependent aperture delay causes distortion in top-plate S/H • Sharp clock edge and small Vin mitigate the delay variation – 23 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Signal Distortion ← 2 nd-order – 24 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu CMOS Switch • Ron still depends on Vin and is sensitive to N/P mismatch • Large parasitic cap due to PMOS switch for symmetric Ron • Clock rising/falling edge alignment – 25 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Clock Bootstrapping • Constant gate overdrive voltage VGS = VDD for the switch • Ron is not dependent on Vin to the first order (body effect? ) • NMOS device only with less parasitic capacitance – 26 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Clock Bootstrapping Ref: A. M. Abo and P. R. Gray, “A 1. 5 -V, 10 -bit, 14. 3 -MS/s CMOS pipeline ADC, ” IEEE Journal of Solid-State Circuits, vol. 34, issue 5, pp. 599 -606, 1999. – 27 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Clock Bootstrapping (Φ=0) – 28 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Clock Bootstrapping (Φ=1) – 29 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Dummy Switch • Initial size of dummy chosen with the assumption of a 50/50 split of Qch; usually (W/L)dummy < ½(W/L)switch in practice • The nonlinear dependence of CI on Zi, CS, and clock rise/fall time makes it difficult to achieve a precise cancellation • Ф_ rising edge must trail Ф falling edge – 30 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Balanced Switch + Dummy • TBW • Parasitics Ref: L. A. Bienstman and H. J. De Man, “An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling, ” IEEE Journal of Solid. State Circuits, vol. 15, issue 6, pp. 1051 -1059, 1980. – 31 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Fully-Differential T/H E. g. fin 0. 5 GHz VDD 1. 8 V tf 0. 1 ns A (Vin) 0. 5 V SDR (SE) 20 -30 d. B SDR (DF) 40 -50 d. B • All even-order distortions cancelled, including the signal-dependent aperture delay-induced distortion • Actual cancellation limited by P/N mismatch (1 -10% typically) – 32 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Bottom-Plate Sampling • AC-ground switch opens slightly earlier than input switches • Signal-independent CF and CI of switch Φe to the first order! • Input switch can be further bootstrapped • Typical for applications of more than 8 -bit resolution • Less tracking bandwidth due to more switches in series • Signal swing at node X is not entirely zero! – 33 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Sample-and-Hold Amplifier (SHA) – 34 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Inverting SHA • Inverting, closed-loop gain determined by the ratio CS/CH • CMOS or bootstrapped switches are required when passing signals with large swing (where? ) – 35 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Inverting SHA (Track-Mode) • CF and CI are independent of Vin and cancelled differentially • Φ 1 e switch is equivalent to two switches of half channel length → faster, less CF and CI – 36 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Inverting SHA (Hold-Mode) • CM? • DM? • For 1 X gain (CS = CH), the feedback factor is about 1/2 • Floating switch Φ 2 in hold-mode → flexible input common mode • Useful for single-ended to differential conversion – 37 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Differential Mode DM half circuit • DM charge transfer is complete – 38 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Common Mode CM half circuit • CM charge is not transferred! – 39 –

Data Converters EECT 7327 Sample-and-Hold Fall 2014 Professor Y. Chiu Flip-Around SHA • Non-inverting, 1 X closed-loop gain • Close-to-unity feedback factor in hold mode • CF/CI independent of Vin and cancelled differentially – 40 –