Data Converters EECT 7327 Comparator Professor Y Chiu

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 CMOS Comparator – 1–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Comparator Transfer characteristic (ideal) Circuit symbol Detects the polarity of the analog input signal and produces a digital output (1 or 0) accordingly – threshold-crossing detector – 2–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Applications • Voltage/current level comparison (A/D conversion) • Digital communication receivers (“slicer” or decision circuit) • Sense amplifier in memory readout circuits • Power electronics with digital control (dc-dc converter) – 3–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Design Considerations • Accuracy (offset, noise, resolution) • Settling time (tracking BW, regeneration speed) • Sensitivity (gain) • Metastability (any decision is better than no decision!) • Overdrive recovery (memory) • CMRR • Power consumption – 4–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Comparator Amplification Clipping • Precise gain and linearity are often unnecessary → simple, low-gain, openloop, wideband amplifiers + latch (positive feedback) • More gain can be derived by cascading multiple gain stages • Built-in sampling function with latched comparators – 5–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Multi-Stage Preamp N stages: – 6–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Step Response – 7–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Optimum N • Given A 0 = Vo/Vi, Nopt can be determined with the above equation • For A 0 < 100, typical N value ranges between 2 and 4 – 8–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Comparison • A higher A 0 (= Vo/Vi) requires a larger N • In comparison, latches regenerate faster than preamps – 9–

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Multi-Stage PA Offset Individual stage Total input-referred – 10 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Input Offset Cancellation • AC coupling at input with input-referred offset stored in C • Two-phase operation, one phase (Φ 2) is used to store offset – 11 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Offset Storage – Φ 2 Closed-loop stability (amplifier in unity-gain feedback) Ref: J. L. Mc. Creary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques. I, ” JSSC, vol. 10, pp. 371 -379, issue 6, 1975. – 12 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Amplifying Phase – Φ 1 • Offset cancellation is incomplete if A is finite • Input AC coupling attenuates signal gain – 13 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 CF and CI of Switches • What’s the optimum phase relationship between Φ 2 and Φ 2'? • Bottom-plate sampling → Φ 2' switches off slightly before Φ 2 (note the operation in this phase is signal independent anyway) – 14 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Output Offset Cancellation • AC coupling at output with offset stored in C • A must be small and well controlled (independent of Vo) • Does not work for high-gain op-amps – 15 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Offset Storage – Φ 2 • Closed-loop stability is not required • CF and CI of Φ 2' gets divided by A when referred to input Ref: R. Poujois and J. Borel, “A low drift fully integrated MOSFET operational amplifier, ” JSSC, vol. 13, pp. 499 -503, issue 4, 1978. – 16 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Amplifying Phase – Φ 1 • Cancellation is complete if A is constant (independent of Vo) • AC coupling at output attenuates signal gain – 17 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Offset Cancellation w/ Auxiliary Input • Gm 1 and Gm 2 are the preamp and latch, respectively • A form of output offset cancellation technique Ref: B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution comparators, ” JSSC, vol. 27, pp. 1916 -1926, issue 12, 1992. – 18 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Offset Sampling • S 3 -S 6 closed • S 1 -S 2 open • Gm 1 and Gm 2 are grounded and the PFB of Gm 2 is disabled • Vos 1 and Vos 2 are amplified by Gm 1 and Gm 2 to appear at Vo • When S 5 & S 6 open (slightly before S 3 & S 4), offset voltage is sampled and stored in C 1 and C 2 • CF/CI of S 5 & S 6 gets divided by (Gm 1/Gm 2) when referred to input – 19 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Comparison • S 3 -S 6 open • S 1 -S 2 closed • Differential input is amplified by Gm 1 to establish an imbalance at the output and AC coupled to the input of Gm 2 • Gm 2 starts regeneration with this imbalance – 20 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Potential Problems • Very complicated → slow conversion speed • C 1 and C 2 and their parasitics add loading to the output • Finite on-resistance of S 5 & S 6 cannot completely break PFB • CF/CI imbalance of S 5 & S 6 can trigger regeneration – 21 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Razavi’s Comparator Even more complicated! – 22 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Overdrive Recovery – 23 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Overdrive Recovery Test “ 0” “ 1” Case II A small input (± 0. 5 LSB) is applied to the comparator input in a cycle right after a full-scale input is applied; the comparator should be able to resolve to the right output in either case → memoryless – 24 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Passive Clamp – 25 – • Limit the output swing with diode clamps → signal-dependent Ro • Clamps add parasitics to the PA output

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Active Reset – 26 – • Kill PA gain with a crowbar switch → time -dependent Ro • Switch adds parasitics to the PA output

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 PA Autozeroing • Two-phase operation, Φ 2 phase is used for offset storage • Autozeroing switch Φ 2' also resets and removes the PA memory – 27 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 CMOS Preamplifier – 28 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Pull-Up • NMOS pull-up suffers from body effect, affecting gain accuracy • PMOS pull-up is free from body effect, but subject to P/N mismatch • Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well, etc. ) don’t track transistors; but it is fast! – 29 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 To Obtain More Gain • Ip diverts current away from PMOS diodes (M 3 & M 4), reducing (W/L)3 • Higher gain w/o CMFB • Needs biasing for Ip • M 3 & M 4 may cut off for large Vin, resulting in a slow recovery – 30 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Bult’s Preamp • NMOS diff. pair loaded with PMOS diodes and PMOS latch (PFB) • High DM gain, low CM gain, good CMRR • Simple, no CMFB • (W/L)34 > (W/L)56 needs to be ensured for stability Ref: K. Bult and A. Buchwald, “An embedded 240 -m. W 10 -b 50 -MS/s CMOS ADC in 1 -mm 2, ” JSSC, vol. 32, pp. 1887 -1895, issue 12, 1997. – 31 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 DM – 32 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 CM – 33 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Song’s Preamp • NMOS diff. pair loaded with PMOS diodes and resistors • High DM gain, low CM gain, good CMRR • Simple, no CMFB • Gain not well-defined Ref: B. -S. Song et al. , “A 1 V 6 b 50 MHz current-interpolating CMOS ADC, ” in Symp. VLSI Circuits, 1999, pp. 79 -80. – 34 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Song’s Preamp DM CM – 35 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 CMOS Latch – 36 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Static Latch • Active pull-up and pulldown → full CMOS logic levels • Very fast! • Q+ and Q- are not well defined in reset mode (Φ = 1) • Large short-circuit current in reset mode • Zero DC current after full regeneration • Very noisy – 37 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Semi-Dynamic Latch • Diode divider disabled in reset mode → less short-circuit current • Pull-up not as fast • Q+ and Q- are still not well defined in reset mode (Φ = 1) • Zero DC current after full regeneration • Still very noisy – 38 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Current-Steering Latch • Constant current → very quite • Higher gain in tracking mode • Cannot produce full logic levels • Fast • Trip point of the inverters – 39 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Dynamic Latch • Zero DC current in reset mode • Q+ and Q- are both reset to “ 0” • Full logic level after regeneration • Slow • No seed voltage Ref: A. Yukawa, “A CMOS 8 -Bit High-Speed A/D Converter IC, ” JSSC, vol. 20, pp. 775 -779, issue 3, 1985. – 40 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Modified Dynamic Latch • Zero DC current in reset mode • Q+ and Q- are both reset to “ 0” • Full logic level after regeneration • Slow • No seed voltage Ref: T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 m. W pipeline A/D converter, ” JSSC, vol. 30, pp. 166 -172, issue 3, 1995. – 41 –

Data Converters EECT 7327 Comparator Professor Y. Chiu Fall 2014 Cho’s Comparator M 1 R and M 2 R added to set the comparator threshold – 42 –