Computer Organization CS 224 Fall 2012 Lesson 26

Computer Organization CS 224 Fall 2012 Lesson 26

Summary of Control Signals coding from green card func 10 0000 10 0010 Not Important op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add sub ori lw sw beq j Reg. Dst 1 ALUSrc 0 Memto. Reg 0 Reg. Write 1 Mem. Write 0 Branch 0 Jump 0 Ext. Op x ALUctr<1: 0> Add 1 0 0 0 x Sub 0 1 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 Add x 0 0 1 0 x Sub x x x 0 0 0 1 x xxx

Multilevel Decoding q 12 -input control will be very large (212 = 4096) q To keep decoder size smaller, decode some control lines in each stage q Since only R-type instructions (with op = 000000) need function field bits, give these to ALU control func op 6 Main Control 6 ALUop Control signals to datapath ALUctr 2 ALU N ALU Control (Local)

Multilevel Decoding: Main Control Table (compare with Fig 4. 22) op Reg. Dst ALUSrc Memto. Reg. Write Mem. Write Branch Jump Ext. Op ALUop<1: 0> 00 0000 R-type 1 0 0 0 x “R-type” 00 1101 10 0011 10 1011 00 0100 00 0010 ori 0 1 0 0 Or lw 0 1 1 1 0 0 0 1 Add sw x 1 x 0 1 0 0 1 Add beq x 0 0 1 0 x Sub j x x x 0 0 0 1 x xx

q ALU used for l l l Load/Store: F = add Branch: F = subtract R-type: F depends on funct field ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR § 4. 4 A Simple Implementation Scheme ALU Control

ALU Control q Assume 2 -bit ALUOp derived from opcode l Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 ori 11 OR immediate XXXXXX or 0001 R-type 10 add 100000 add 0010 subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001 set-on-less-than 101010 set-on-less-than 0111

The Main Control Unit q Control signals derived from instruction R-type 0 rs 31: 26 Load/ Store 35 or 43 Branch 4 31: 26 25: 21 rs opcode 25: 21 always read rd 20: 16 rt 25: 21 rs 31: 26 rt shamt 15: 11 10: 6 funct 5: 0 address 20: 16 rt 15: 0 address 20: 16 read, except for load 15: 0 write for R -type and load sign-extend add

Datapath With Control

R-Type Instruction

Load Instruction

Branch-on-Equal Instruction

Implementing Jumps 2 Jump address 31: 26 q Jump uses word address q Update PC with concatenation of l Top 4 bits of old PC 26 -bit jump address l 00 l q 25: 0 Need an extra control signal decoded from opcode

Datapath With Jumps Added Figure 4. 24

Putting It All Together ALUop Reg. Dst op Main 6 Control Instr[31: 26] Rs Rt 5 5 Extender 16 Zero 1 32 Ext. Op Imm 16 Memto. Reg Mem. Wr 0 32 Data In 32 ALUSrc Rs Rd Clk Wr. En Adr Data Memory 32 MUX bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 imm 16 Rt ALUctr [0: 15] Clk MUX 32 Clk Instruction Fetch Unit Jump Mux 0 5 Instruction[31: 0] ALU bus. W : Branch [11: 15] Reg. Wr func Instr[5: 0] 6 [16: 20] 1 ALUctr Control 3 [21: 25] Reg. Dst ALUSrc Rt Rd 3 1

Single Cycle Processor q q Advantages l Single cycle per instruction makes logic and clock simple l All machines would have a CPI of 1 Disadvantages l Inefficient utilization of memory and functional units since different instructions take different lengths of time - Each functional unit is used only once per clock cycle - e. g. ALU only computes values a small amount of the time l Cycle time is the worst case path long cycle times! - Load instruction – – – – l PC CLK-to-Q + instruction memory access time + register file access time + ALU delay + data memory access time + register file setup time + clock skew All machines would have a CPI of 1, with cycle time set by the longest instruction!

Performance Issues q Longest delay determines clock period l l Critical path: load instruction Instruction memory register file ALU data memory register file q Not feasible to vary period for different instructions q Violates design principle l q Making the common case fast We will improve performance by pipelining

Summary § Single cycle datapath => CPI=1, CCT => long § 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic § Control is the hard part Processor § MIPS makes control easier • Instructions same size Input Control Memory • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates Datapath Output