ANALOG TO DIGITAL CONVERTERS ADCS ETC Eric Prebys

ANALOG TO DIGITAL CONVERTERS (ADCS), ETC Eric Prebys

P 116 B - Winter 2020 P 116 B - ADCs Digression: Priority Encoding • A priority encoding, encoded a binary number corresponding to the highest priority input bit that’s set

P 116 B - Winter 2020 P 116 B - ADCs Special Case: only one input active • If one and only one input is asserted at a time the circuit is very simple. Example: 4 -2 (exclusive) priority decoder • Output not meaningful if more than one input is asserted • Have each disable all lower inputs

P 116 B - Winter 2020 P 116 B - ADCs General 4 -2 Priority Encoder

P 116 B - Winter 2020 P 116 B - ADCs 8 -3 Priority Encoder with Realistic Components

P 116 B - Winter 2020 P 116 B - ADCs Back to ADCs • The simplest type of ADC is a “flash” or “parallel” ADC • This is similar to the resistor ladder DAC in reverse. • A n-bit ADC works by creating a 2 n point resistive chain, comparing the input to these levels, and feeding the result into a priority encoder. • Simple and fast, but quickly get lots of comparators • Pure, single-step, flash ADCs are generally only available up to 8 -bit

P 116 B - Winter 2020 Example: Maxim MAX 1151 • 8 -bit resolution • 750 Ms/sec P 116 B - ADCs

P 116 B - Winter 2020 P 116 B - ADCs Modified Flash Encoders • We can we can do flash encoders in multiples stages • Flash encode higher order bits • Feed these into a DAC • Subtract the output of the DAC from the signal • Flash encode lower order bits

P 116 B - Winter 2020 P 116 B - ADCs Example: TI TLC 0820 • 8 -bit modified flash, using 2 4 -bit flash ADCs • Note that we have introduced three steps of latency relative to a simple flash: DAC+subtraction+LSB flash

P 116 B - Winter 2020 P 116 B - ADCs Latency vs. Throughput • The time from a valid input (+CONVERT signal) until a valid output is referred to as the “latency” • In the examples we’ve given, we need to complete one digitization before accepting another sample • In most practical application, we’re more interested in the “throughput”; that is, the total number of samples we can process in a given time, regardless of the latency • Design multi-stage converters such that we can begin to work on the next sample before completing the first • “pipelining”

P 116 B - Winter 2020 P 116 B - ADCs Example: 12 -bit from 4 3 -bit pipelines stages • The output of each stage is latched and feeds into the next stage

P 116 B - Winter 2020 Successive Approximation • Algorithm 1. Set highest order remaining bit (beginning with MSB) 2. Feed all set bits into a DAC 3. Is input signal > DAC output? • yes: leave bit set • No: clear bit 4. GOTO 1 • Successive approximation ADCs can also be pipelined P 116 B - ADCs

P 116 B - Winter 2020 P 116 B - ADCs Charge Redistribution DACs • In successive approximation ADCs, the R-2 R resistor ladder is often replace by a “charge- redistribution” scheme • Capacitors are a lot easier to implement on chips than resistors • Can do both the DAC and the comparison in one stage.

P 116 B - Winter 2020 P 116 B - ADCs Understanding Charge Redistribution • Imagine I have two grounded capacitors in parallel, charged to a voltage V • If I move the grounded leg of C 1 to Vref, then the total charge that will flow into the pair is • And the center voltage will go to • If I were to ground C 1 again, every thing would go back where it started

P 116 B - Winter 2020 P 116 B - ADCs Capacitors in an n-bit Distributed Capacitor DAC • For bit i • So switching capacitor i from GND to Vref, changes the voltage by

P 116 B - Winter 2020 P 116 B - ADCs Back to the ADC (3 -bit example) • We start with all caps grounded and VX=-Vin • We switch the MSB to Vref • This adds 22/23*Vref=Vref/2 to VX • Is VX<0 • yes: Vin>Vref /2 set bit 2 (leave switch set to Vref) • no: Vin<Vref clear bit 2 (switch set back to GND) • Continue to next bit and repeat

P 116 B - Winter 2020 P 116 B - ADCs Integrating Converter • A single slope integrating convert begins to charge a capacitor at a known rate, and counts the time until it reaches the input signal. • Slow, but can be cheap with very high precision

P 116 B - Winter 2020 P 116 B - ADCs Variation: Dual-Slope Conversion • In this technique, a capacitor is charged at a rate proportional to the input voltage and discharged at a constant rate. • The discharge time is proportional to the input. Advantages • Shorter stability time on the input • Uncertainties in capacitance cancel out

P 116 B - Winter 2020 P 116 B - ADCs Undersampling and Aliasing • As we said before, sampling at N samples/second has a bandwidth of N/2 Hz, but what if we try to digitize something with a higher frequency

P 116 B - Winter 2020 P 116 B - ADCs Aliasing (cont’d) • In general, aliasing will bring regions symmetrically oriented around multiples of the sampling frequency into our bandpass range. • We can use this to our advantage to shift high frequency content into our baseband range (more about this when we talk about FM processing) • In general, however, it can cause problems

P 116 B - Winter 2020 P 116 B - ADCs Aliasing and Noise • No filter is perfect, and aliasing can bring the unwanted components into our bandpass region

P 116 B - Winter 2020 P 116 B - ADCs Oversampling and Aliasing • Filtering and sampling at a higher rate can reduce the effect of aliased noise on our band of interest • This is the reason audio recording samples at >2*20 k. Hz

P 116 B - Winter 2020 P 116 B - ADCs Oversampling and Resolution • If I feed a DC signal into an ADC, then no amount of sampling will increase the resolution • On the other hand, if the signal is distributed over many values, oversampling and averaging can, eg, distinguish

P 116 B - Winter 2020 P 116 B - ADCs Trading Bits for Rate • Like any statistical process, the resolution will improve as • Since each bit corresponds to a factor of two in resolution, I can gain 1 bit of precision for every factor of 4 in sampling rate • Example • AD 9260: 8 x oversampling -> 14 bits -> 16 bits • How far can we take this?

P 116 B - Winter 2020 P 116 B - ADCs DS 1 -bit Encoding/Decoding • A DS is encoder is essentially a successive approximation 1 -bit ADC

P 116 B - Winter 2020 P 116 B - ADCs Oversampling in DS Converters • By our usual rules, we would have to sample many orders of magnitude over the Nyquist frequency, but because this system affects noise in different parts of the bandwidth differently, we can usually get away with 64 x oversampling, particularly if multiple stages are used. • DS Conversers are normally used in audio applications, because they are very monotonic and extremely cheap.

P 116 B - Winter 2020 P 116 B - ADCs Considerations in Digitizing Signals • Issues • Many signals that come out of detectors are short compared to the stability, and may also have varying delays • In general, we don’t read out data unless an event satisfies some “trigger” condition, which typically comes after the signals. • General solution • Integrate • “Sample and Hold”

P 116 B - Winter 2020 P 116 B - ADCs Integrating Signals • A simple integrator can preserve a short signal until it can be digitized • Many variations on this theme

P 116 B - Winter 2020 P 116 B - ADCs Sample and Hold Circuit • A sample and hold circuit uses a low impedance buffer to charge a capacitor to follow an input signal. • A HOLD signal opens a switch, such that the capacitor retains the value of the signal at a particular time.

P 116 B - Winter 2020 P 116 B - ADCs Digital Signal Processing • In modern systems, particularly those with low numbers of channels, analog signals are digitized at high rate and processed digitally

P 116 B - Winter 2020 Example: PMT Outputs Use difference between adjacent samples to find peaks For each peak, encode: • Time (clock cycle) • Peak value • Integrated value • Time over threshold Could optionally store a fixed number of samples for each detected peak P 116 B - ADCs

P 116 B - Winter 2020 P 116 B - ADCs TDCs • Time-to-Digital Converters (TDCs) are a special type of ADC that converts a time interval to a number. • Applications include • Discriminating “in-time” from “out-of-time” signals • Measuring time of flight, to determine velocity • Measuring ionization drift time to determine position • Drift chambers • Time projection chambers (TPCs) • Unlike a lot of the other technologies we discuss, TDCs have limited use outside of research

P 116 B - Winter 2020 P 116 B - ADCs Counting TDCs • The simplest TDCs are just counters that count clock cycles between a START and STOP signal • Easy to implement “multi-hit” TDCs • These are practical up to about 1 GHz (ns resolution)

P 116 B - Winter 2020 P 116 B - ADCs Charge Integration TDC • A switch is closed during the timing interval, causing a capacitor to charge at a constant rate. • The value of the capacitor is digitized by an ADC • Can reach resolutions on the order of ps • To go lower than a picosecond, generally need to use more sophisticated methods

P 116 B - Winter 2020 P 116 B - ADCs Dual Slope TDCs (Time Stretchers) • One technique involves measuring time by charging a capacitor very quickly, then discharging it much more slowly, measuring the time it takes to return to zero. • The time of the second ramp is proportional to the first, but can be measured with a counter (or perhaps in a separate module)

P 116 B - Winter 2020 P 116 B - ADCs General Modes of Operation • START/STOP • One signal starts the TDC, another one stops it • Example: Time of Flight. The first counter starts the TDC, the second stops it • Common START • A common LIVE or GATE signal is sent out, starting all TDCs • Individual signals stop TDCs • No hit – channel overflows and resets • Common STOP • Individual hits start individual TDCs • All are stopped if an experimental trigger condition is satisfied • Ring counter common trigger (only works with counting TDCs) • A counter counts continuously, starting over when it hits the maximum • The values at hit times are stored • The trigger time is stored • Can record times both before and after common trigger

P 116 B - Winter 2020 P 116 B - ADCs Time Slewing • The simplest way to trigger a TDC is with a simple threshold; however, this will introduce an amplitudedependent shift • One solution is to measure the pulse-height and correct for this after the fact, but what I don’t measure the pulse height (or need more accurate real time timing?

P 116 B - Winter 2020 P 116 B - ADCs Constant Fraction Discriminator • In most cases, the pulse shape is more or less independent of the amplitude. • We will therefore get a more accurate measure of the time by measuring when it hits a certain fraction of the maximum, rather than a fixed threshold • Constant fraction discriminators work by adding an attenuated version of the signal to a delayed and inverted version of the signal: will cross zero at a fixed fraction of the total