inst eecs berkeley educs 61 c UC Berkeley
inst. eecs. berkeley. edu/~cs 61 c UC Berkeley CS 61 C : Machine Structures Lecture 28 – CPU Design : Pipelining to Improve Performance 2006 -11 -03 Lecturer SOE Dan Garcia www. cs. berkeley. edu/~ddgarcia 100 Msites! Sometimes it’s nice to stop and reflect. The web was recently measured as having 100 million sites. How did we live without it? It’s changed MY life; has it changed yours? Ans: Duh! www. cnn. com/2006/TECH/internet/11/01/100 millionwebsites CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (1) Garcia, Fall 2006 © UCB
Review: Single cycle datapath ° 5 steps to design a processor • 1. Analyze instruction set datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor Input • 5. Assemble the control logic Control ° Control is the hard part ° MIPS makes that easier Memory Datapath • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (2) Output Garcia, Fall 2006 © UCB
How We Build The Controller Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr[0] ALUctr[1] opcode func = add + sub = ori + lw + sw add = lw sub ori = add + sub + ori + lw lw = sw “OR” logic “AND” logic sw = beq = jump = lw + sw = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR) = or Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr[0] ALUctr[1] where, rtype = ~op 5 ~op 4 ~op 3 ~op 2 ori = ~op 5 ~op 4 op 3 op 2 lw = op 5 ~op 4 ~op 3 ~op 2 sw = op 5 ~op 4 op 3 ~op 2 beq = ~op 5 ~op 4 ~op 3 op 2 jump = ~op 5 ~op 4 ~op 3 ~op 2 ~op 1 ~op 0, ~op 1 op 0 ~op 1 ~op 0 How do we implement this in gates? add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func 1 ~func 0 sub = rtype func 5 ~func 4 ~func 3 ~func 2 func 1 ~func 0 CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (3) Garcia, Fall 2006 © UCB
Processor Performance • Can we estimate the clock rate (frequency) of our single-cycle processor? We know: • 1 cycle per instruction • lw is the most demanding instruction. • Assume approximate delays for major pieces of the datapath: § Instr. Mem, ALU, Data Mem : 2 ns each, regfile 1 ns § Instruction execution requires: 2 + 1 + 2 + 1 = 8 ns § 125 MHz • What can we do to improve clock rate? • Will this improve performance as well? • We want increases in clock rate to result in programs executing quicker. CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (4) Garcia, Fall 2006 © UCB
Gotta Do Laundry ° Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put away A B C D ° Washer takes 30 minutes ° Dryer takes 30 minutes ° “Folder” takes 30 minutes ° “Stasher” takes 30 minutes to put clothes into drawers CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (5) Garcia, Fall 2006 © UCB
Sequential Laundry 6 PM 7 T a s k O r d e r A 8 9 10 11 12 1 2 AM 30 30 30 30 Time B C D • Sequential laundry takes 8 hours for 4 loads CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (6) Garcia, Fall 2006 © UCB
Pipelined Laundry 6 PM 7 T a s k 8 9 3030 30 30 10 11 12 1 2 AM Time A B C O D r d e • Pipelined r laundry takes 3. 5 hours for 4 loads! CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (7) Garcia, Fall 2006 © UCB
General Definitions • Latency: time to completely execute a certain task • for example, time to read a sector from disk is disk access time or disk latency • Throughput: amount of work that can be done over a period of time CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (8) Garcia, Fall 2006 © UCB
Pipelining Lessons (1/2) 6 PM T a s k 8 9 Time 30 30 A B O r d e r 7 C D • Pipelining doesn’t help latency of single task, it helps throughput of entire workload • Multiple tasks operating simultaneously using different resources • Potential speedup = Number pipe stages • Time to “fill” pipeline and time to “drain” it reduces speedup: 2. 3 X v. 4 X in this example CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (9) Garcia, Fall 2006 © UCB
Pipelining Lessons (2/2) • Suppose new Washer takes 20 6 PM 7 8 9 minutes, new Time T Stasher takes 20 a 30 30 minutes. How s A much faster is k pipeline? B O r d e r C D • Pipeline rate limited by slowest pipeline stage • Unbalanced lengths of pipe stages reduces speedup CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (10) Garcia, Fall 2006 © UCB
Steps in Executing MIPS 1) IFtch: Instruction Fetch, Increment PC 2) Dcd: Instruction Decode, Read Registers 3) Exec: Mem-ref: Calculate Address Arith-log: Perform Operation 4) Mem: Load: Read Data from Memory Store: Write Data to Memory 5) WB: Write Data Back to Register CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (11) Garcia, Fall 2006 © UCB
Pipelined Execution Representation Time IFtch Dcd Exec Mem WB IFtch Dcd Exec Mem WB • Every instruction must take same number of steps, also called pipeline “stages”, so some will go idle sometimes CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (12) Garcia, Fall 2006 © UCB
+4 1. Instruction Fetch rs rt ALU Data memory rd registers PC instruction memory Review: Datapath for MIPS imm 5. Write 2. Decode/ 3. Execute 4. Memory Back Register Read • Use datapath figure to represent pipeline IFtch Dcd Exec Mem WB Reg CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (13) ALU I$ D$ Reg Garcia, Fall 2006 © UCB
Graphical Pipeline Representation (In Reg, right half highlight read, left half write) Time (clock cycles) Reg D$ Reg I$ Reg ALU I$ D$ ALU Reg ALU I$ ALU I n s Load t Add r. Store O Sub r d Or e r D$ CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (14) Reg Garcia, Fall 2006 © UCB
Example • Suppose 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write; compute instr rate • Nonpipelined Execution: • lw : IF + Read Reg + ALU + Memory + Write Reg = 2 + 1 + 2 + 1 = 8 ns • add: IF + Read Reg + ALU + Write Reg = 2 + 1 + 2 + 1 = 6 ns (recall 8 ns for single-cycle processor) • Pipelined Execution: • Max(IF, Read Reg, ALU, Memory, Write Reg) = 2 ns CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (15) Garcia, Fall 2006 © UCB
Pipeline Hazard: Matching socks in later load 6 PM 7 T a s k 8 9 3030 30 30 A 10 11 12 1 2 AM Time bubble B C O D r d E e r F A depends on D; stall since folder tied up CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (16) Garcia, Fall 2006 © UCB
Administrivia • We know the readers are behind, a fire has been lit, and they say they’re on it • No lecture next Friday • Those who have lab on Friday should come to any lab in Thursday and do it • Worst case, you can do it at home and get it checked off next week CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (17) Garcia, Fall 2006 © UCB
Problems for Pipelining CPUs • Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle • Structural hazards: HW cannot support some combination of instructions (single person to fold and put clothes away) • Control hazards: Pipelining of branches causes later instruction fetches to wait for the result of the branch • Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) • These might result in pipeline stalls or “bubbles” in the pipeline. CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (18) Garcia, Fall 2006 © UCB
Structural Hazard #1: Single Memory (1/2) Time (clock cycles) ALU I n I$ D$ Reg s Load I$ D$ Reg t Instr 1 r. I$ D$ Reg Instr 2 O I$ D$ Reg Instr 3 r I$ D$ Reg d Instr 4 e r Read same memory twice in same clock cycle ALU ALU CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (19) Garcia, Fall 2006 © UCB
Structural Hazard #1: Single Memory (2/2) • Solution: • infeasible and inefficient to create second memory • (We’ll learn about this more next week) • so simulate this by having two Level 1 Caches (a temporary smaller [of usually most recently used] copy of memory) • have both an L 1 Instruction Cache and an L 1 Data Cache • need more complex hardware to control when both caches miss CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (20) Garcia, Fall 2006 © UCB
Structural Hazard #2: Registers (1/2) Reg D$ Reg I$ Reg ALU I$ D$ ALU Reg ALU I$ ALU O Instr 2 r Instr 3 d e Instr 4 r Time (clock cycles) ALU I n s t sw r. Instr 1 D$ Reg Can we read and write to registers simultaneously? CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (21) Garcia, Fall 2006 © UCB
Structural Hazard #2: Registers (2/2) • Two different solutions have been used: 1) Reg. File access is VERY fast: takes less than half the time of ALU stage § Write to Registers during first half of each clock cycle § Read from Registers during second half of each clock cycle 2) Build Reg. File with independent read and write ports • Result: can perform Read and Write during same clock cycle CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (22) Garcia, Fall 2006 © UCB
Peer Instruction A. Thanks to pipelining, I have reduced the time it 1: took me to wash my shirt. 2: B. Longer pipelines are always a win (since less 3: work per stage & a faster clock). 4: 5: C. We can rely on compilers to help us avoid data 6: hazards by reordering instrs. 7: 8: CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (23) ABC FFF FFT FTF FTT TFF TFT TTF TTT Garcia, Fall 2006 © UCB
Things to Remember • Optimal Pipeline • Each stage is executing part of an instruction each clock cycle. • One instruction finishes during each clock cycle. • On average, execute far more quickly. • What makes this work? • Similarities between instructions allow us to use same stages for all instructions (generally). • Each stage takes about the same amount of time as all others: little wasted time. CS 61 C L 28 CPU Design : Pipelining to Improve Performance I (25) Garcia, Fall 2006 © UCB
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