inst eecs berkeley educs 61 c UC Berkeley
inst. eecs. berkeley. edu/~cs 61 c UC Berkeley CS 61 C : Machine Structures Lecture 27 – Single-Cycle CPU Control 2006 -11 -01 Lecturer SOE Dan Garcia www. cs. berkeley. edu/~ddgarcia Wireless High Definition? Several companies will be working on a “Wireless. HD” standard, which will allow HD output devices like laptops, DVD players, video cameras and video games to send HD content @ 5 GB/s! news. com/Wireless+HD+specification+due+in+2007/2100 -1039_3 -6130942. html CS 61 C L 27 Single Cycle CPU Control (1) Garcia, Fall 2006 © UCB
Putting it All Together: A Single Cycle Datapath Reg. Dst 32 Equal 0 5 5 5 Rw Ra Rb Reg. File bus. A bus. B 32 16 Extender imm 16 Memto. Reg Mem. Wr Rs Rt clk ALUctr 32 = ALU bus. W PC PC Ext Adder Mux 00 Reg. Wr Adder 4 Rt Rd Imm 16 Rd Rt 1 Instruction<31: 0> <0: 15> n. PC_sel Rs <11: 15> Adr <16: 20> <21: 25> Inst Memory 0 32 1 32 Data In clk 32 0 Wr. En Adr Data Memory 1 imm 16 Ext. Op CS 61 C L 27 Single Cycle CPU Control (2) ALUSrc Garcia, Fall 2006 © UCB
An Abstract View of the Implementation Ideal Instruction Memory PC clk 32 Instruction Rd Rs Rt 5 5 5 Rw Ra Rb Register File clk Control Signals Conditions A 32 ALU Next Address Instruction Address Control B 32 32 Data Addr Ideal Data Memory Data Out Data In clk Datapath CS 61 C L 27 Single Cycle CPU Control (3) Garcia, Fall 2006 © UCB
An Abstract View of the Critical Path Ideal Instruction Memory PC clk 32 Instruction Rd Rs Rt 5 5 5 Rw Ra Rb Register File clk CS 61 C L 27 Single Cycle CPU Control (4) (Assumes a fast controller) A 32 ALU Next Address Instruction Address Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32 -bit Add + Data Memory Access Time + Stable Time for Register File Write B 32 32 Data Addr Ideal Data Memory Data In clk Garcia, Fall 2006 © UCB
Summary: A Single Cycle Datapath Instruction<31: 0> Rs Rt Rd Imm 16 ALUctr Memto. Reg Rd Rt 1 Reg. Wr 0 5 Rs Rt 5 bus. B 32 16 Extender clk imm 16 bus. A Ext. Op CS 61 C L 27 Single Cycle CPU Control (5) 32 Mem. Wr = ALU Reg. File 32 zero 5 Rw Ra Rb bus. W <0: 15> Reg. Dst <11: 15> clk <16: 20> instr fetch unit n. PC_sel <21: 25> • We have everything except control signals 0 32 1 32 Data In clk 32 0 Wr. En Adr Data Memory 1 ALUSrc Garcia, Fall 2006 © UCB
Recap: Meaning of the Control Signals “+4” 0 PC <– PC + 4 “br” 1 PC <– PC + 4 + “n”=next {Sign. Ext(Im 16) , 00 } • Later in lecture: higher-level connection between mux and branch condition • n. PC_sel: Inst Address 00 0 PC Mux Adder PC Ext imm 16 CS 61 C L 27 Single Cycle CPU Control (6) n. PC_sel Adder 4 1 clk Garcia, Fall 2006 © UCB
Recap: Meaning of the Control Signals • Ext. Op: “zero”, “sign” ° Mem. Wr: 1 write memory ° Memto. Reg: 0 ALU; 1 Mem • ALUsrc: 0 reg. B; 1 immed ° Reg. Dst: 0 “rt”; 1 “rd” • ALUctr: “ADD”, “SUB”, “OR°”Reg. Wr: 1 write register ALUctr Reg. Dst Rd Rt 1 Reg. Wr 0 Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Ext. Op CS 61 C L 27 Single Cycle CPU Control (7) Extender clk 32 0 ALU bus. W Memto. Reg Mem. Wr 32 0 32 Wr. En Adr 1 32 Data In ALUSrc clk Data Memory 1 Garcia, Fall 2006 © UCB
RTL: The Add Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits add rd, rs, rt • MEM[PC] Fetch the instruction from memory • R[rd] = R[rs] + R[rt] The actual operation • PC = PC + 4 Calculate the next instruction’s address CS 61 C L 27 Single Cycle CPU Control (8) Garcia, Fall 2006 © UCB
Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction = MEM[PC] • same for all instructions Inst Memory n. PC_sel Inst Address 00 Adder 4 Instruction<31: 0> PC Mux Adder PC Ext clk imm 16 CS 61 C L 27 Single Cycle CPU Control (9) Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Add 31 26 op 21 16 rs 11 rt rd 6 shamt funct R[rd] = R[rs] + R[rt] 5 5 5 bus. A Rw Ra Rb Reg. File 32 bus. B 32 imm 16 16 Extender clk Ext. Op=x CS 61 C L 27 Single Cycle CPU Control (10) Rs Rt Rd Imm 16 zero ALUctr=ADD Memto. Reg=0 Mem. Wr=0 32 = ALU bus. W 0 32 1 32 <0: 15> Rs Rt <11: 15> Reg. Wr=1 <16: 20> 0 <21: 25> Rd Rt 1 Instruction<31: 0> instr fetch unit n. PC_sel=+4 Reg. Dst=1 clk 0 Data In ALUSrc=0 clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
Instruction Fetch Unit at the End of Add • PC = PC + 4 • This is the same for all instructions except: Branch and Jump Inst Memory n. PC_sel=+4 Inst Address 00 Adder 4 PC Mux Adder PC Ext clk imm 16 CS 61 C L 27 Single Cycle CPU Control (11) Garcia, Fall 2006 © UCB
Single Cycle Datapath during Or Immediate? 31 26 21 op 16 rs 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Ext. Op= CS 61 C L 27 Single Cycle CPU Control (12) Extender clk Rs Rt Rd Imm 16 zero ALUctr= Memto. Reg= Mem. Wr= 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr= 0 <11: 15> 1 clk <16: 20> Rd Rt <21: 25> n. PC_sel= Reg. Dst= Instruction<31: 0> instr fetch unit Data In ALUSrc= clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
Single Cycle Datapath during Or Immediate? 31 26 21 op 16 rs 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] 5 Rs Rt 5 5 bus. A Rw Ra Rb Reg. File 32 32 16 Extender clk imm 16 bus. B Ext. Op=zero CS 61 C L 27 Single Cycle CPU Control (13) Rs Rt Rd Imm 16 zero ALUctr=OR Memto. Reg=0 Mem. Wr=0 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr=1 <11: 15> 0 <16: 20> Rd Rt <21: 25> n. PC_sel=+4 Reg. Dst=0 clk 1 Instruction<31: 0> instr fetch unit Data In ALUSrc=1 clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Load? 31 26 21 op 16 rs 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Ext. Op= CS 61 C L 27 Single Cycle CPU Control (14) Extender clk Rs Rt Rd Imm 16 Zero ALUctr= Memto. Reg= Mem. Wr= 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr= 0 <11: 15> 1 clk <16: 20> Rd Rt <21: 25> n. PC_sel= Reg. Dst= Instruction<31: 0> instr fetch unit Data In ALUSrc= clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Load 31 26 21 op 16 rs 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} 5 Rs Rt 5 5 bus. A Rw Ra Rb Reg. File 32 32 16 Extender clk imm 16 bus. B Ext. Op=sign CS 61 C L 27 Single Cycle CPU Control (15) Rs Rt Rd Imm 16 zero ALUctr=ADD Memto. Reg=1 Mem. Wr=0 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr=1 <11: 15> 0 <16: 20> Rd Rt <21: 25> n. PC_sel=+4 Reg. Dst=0 clk 1 Instruction<31: 0> instr fetch unit Data In ALUSrc=1 clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Store? 31 26 21 op 16 rs 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Ext. Op= CS 61 C L 27 Single Cycle CPU Control (16) Extender clk Rs Rt Rd Imm 16 zero ALUctr= Memto. Reg= Mem. Wr= 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr= 0 <11: 15> 1 clk <16: 20> Rd Rt <21: 25> n. PC_sel= Reg. Dst= Instruction<31: 0> instr fetch unit Data In ALUSrc= clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Store 31 26 21 op 16 rs 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] 5 Rs Rt 5 5 bus. A Rw Ra Rb Reg. File 32 32 16 Extender clk imm 16 bus. B Ext. Op=sign CS 61 C L 27 Single Cycle CPU Control (17) Rs Rt Rd Imm 16 zero ALUctr=ADD Memto. Reg=x Mem. Wr=1 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr=0 <11: 15> 0 <16: 20> Rd Rt <21: 25> n. PC_sel=+4 Reg. Dst=x clk 1 Instruction<31: 0> instr fetch unit Data In ALUSrc=1 clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Branch? 31 26 21 op 16 rs 0 rt immediate • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Ext. Op= CS 61 C L 27 Single Cycle CPU Control (18) Extender clk Rs Rt Rd Imm 16 zero ALUctr= Memto. Reg= Mem. Wr= 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr= 0 <11: 15> 1 clk <16: 20> Rd Rt <21: 25> n. PC_sel= Reg. Dst= Instruction<31: 0> instr fetch unit Data In ALUSrc= clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
The Single Cycle Datapath during Branch 31 26 21 op 16 rs 0 rt immediate • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Rs Rt 5 5 5 bus. A Rw Ra Rb Reg. File 32 bus. B 32 imm 16 16 Extender clk Ext. Op=x CS 61 C L 27 Single Cycle CPU Control (19) Rs Rt Rd Imm 16 zero ALUctr=SUB Memto. Reg=x Mem. Wr=0 32 = ALU bus. W 0 32 1 32 <0: 15> Reg. Wr=0 <11: 15> 0 <16: 20> Rd Rt <21: 25> n. PC_sel=br Reg. Dst=x clk 1 Instruction<31: 0> instr fetch unit Data In ALUSrc=0 clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
Instruction Fetch Unit at the End of Branch 31 26 op 21 rs 16 rt 0 immediate • if (Zero == 1) then PC = PC + 4 + Sign. Ext[imm 16]*4 ; else PC = PC + 4 Inst Memory n. PC_sel Adr Zero 0 Mux PC Adder PC Ext imm 16 Adder 4 00 MUX ctrl n. PC_sel 1 Instruction<31: 0> • What is encoding of n. PC_sel? • Direct MUX select? • Branch inst. / not branch • Let’s pick 2 nd option Q: What logic gate? clk CS 61 C L 27 Single Cycle CPU Control (20) Garcia, Fall 2006 © UCB
Step 4: Given Datapath: RTL -> Control Instruction<31: 0> Rd <0: 15> Rs <11: 15> Rt <16: 20> Op Fun <21: 25> <0: 5> Adr <26: 31> Inst Memory Imm 16 Control n. PC_sel Reg. Wr Reg. Dst Ext. Op ALUSrc ALUctr Mem. Wr Memto. Reg DATA PATH CS 61 C L 27 Single Cycle CPU Control (21) Garcia, Fall 2006 © UCB
A Summary of the Control Signals (1/2) inst Register Transfer add R[rd] R[rs] + R[rt]; PC + 4 ALUsrc = Reg. B, ALUctr = “ADD”, Reg. Dst = rd, Reg. Wr, n. PC_sel = “+4” sub R[rd] R[rs] – R[rt]; PC + 4 ALUsrc = Reg. B, ALUctr = “SUB”, Reg. Dst = rd, Reg. Wr, n. PC_sel = “+4” ori R[rt] R[rs] + zero_ext(Imm 16); PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “OR”, Reg. Dst = rt, Reg. Wr, n. PC_sel =“+4” lw R[rt] MEM[ R[rs] + sign_ext(Imm 16)]; PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, Memto. Reg, Reg. Dst = rt, Reg. Wr, n. PC_sel = “+4” sw MEM[ R[rs] + sign_ext(Imm 16)] R[rs]; PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, Mem. Wr, n. PC_sel = “+4” beq if ( R[rs] == R[rt] ) then PC + sign_ext(Imm 16)] || 00 else PC + 4 n. PC_sel = “br”, ALUctr = “SUB” CS 61 C L 27 Single Cycle CPU Control (22) Garcia, Fall 2006 © UCB
A Summary of the Control Signals (2/2) See Appendix A func 10 0000 10 0010 We Don’t Care : -) op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 ALUSrc Memto. Reg. Write Mem. Write add 1 0 0 1 0 sub 1 0 0 1 0 ori 0 1 0 lw 0 1 1 1 0 sw x 1 x 0 1 n. PCsel Jump Ext. Op ALUctr<2: 0> 0 0 x Add 0 0 x Subtract 0 0 0 Or 0 0 1 Add Reg. Dst 31 26 21 16 R-type op rs rt I-type op rs rt J-type op CS 61 C L 27 Single Cycle CPU Control (23) 11 rd jump x x x 0 0 1 0 x 0 1 x xxx Subtract 6 shamt immediate target address beq x 0 0 0 funct add, sub ori, lw, sw, beq jump Garcia, Fall 2006 © UCB
Boolean Expressions for Controller Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr[0] ALUctr[1] = add + sub = ori + lw + sw = lw = add + sub + ori + lw = sw = beq = jump = lw + sw = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR) = or where, rtype = ~op 5 ~op 4 ~op 3 ~op 2 ori = ~op 5 ~op 4 op 3 op 2 lw = op 5 ~op 4 ~op 3 ~op 2 sw = op 5 ~op 4 op 3 ~op 2 beq = ~op 5 ~op 4 ~op 3 op 2 jump = ~op 5 ~op 4 ~op 3 ~op 2 ~op 1 ~op 0, ~op 1 op 0 ~op 1 ~op 0 How do we implement this in gates? add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func 1 ~func 0 sub = rtype func 5 ~func 4 ~func 3 ~func 2 func 1 ~func 0 CS 61 C L 27 Single Cycle CPU Control (24) Garcia, Fall 2006 © UCB
Controller Implementation opcode func “AND” logic CS 61 C L 27 Single Cycle CPU Control (25) add sub ori lw sw beq jump “OR” logic Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr[0] ALUctr[1] Garcia, Fall 2006 © UCB
Peer Instruction A. Our ALU is a synchronous device B. We should use the main ALU to compute PC=PC+4 C. The ALU is inactive for memory reads or writes. CS 61 C L 27 Single Cycle CPU Control (26) 1: 2: 3: 4: 5: 6: 7: 8: ABC FFF FFT FTF FTT TFF TFT TTF TTT Garcia, Fall 2006 © UCB
Summary: Single-cycle Processor ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic Processor • Formulate Logic Equations • Design Circuits Control Memory Datapath CS 61 C L 27 Single Cycle CPU Control (27) Input Output Garcia, Fall 2006 © UCB
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