Hardware Description Language Logic Design using Verilog TsungChu

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Hardware Description Language -- Logic Design using Verilog Tsung-Chu Huang Dept. of Electronic Eng.

Hardware Description Language -- Logic Design using Verilog Tsung-Chu Huang Dept. of Electronic Eng. National Changhua University of Ed. Email: tch@cc. ncue. edu. tw 2011/11/17 HDL T. -C. Huang / NCUE Fall 2005 1

Prototyping-on-Demand Ø Considerations of Your Designs 1. 2. 3. 4. 5. 6. Functions (with

Prototyping-on-Demand Ø Considerations of Your Designs 1. 2. 3. 4. 5. 6. Functions (with RAM, ROM, PLL, AD/DA, other IP) Performance/Speed Gate Count Power Clocks Size Ø Evaluate Devices from the Webs 1. Xilinx: Virtex, Spartan … 2. Altera: Stratix, Cyclone, FLEX, MAX … 3. Actel … HDL T. -C. Huang / NCUE Fall 2005 2

Tutorial of FPGA Rapid Prototyping Ø Taking Altera/Quartus II as an Example 1. 2.

Tutorial of FPGA Rapid Prototyping Ø Taking Altera/Quartus II as an Example 1. 2. 3. 4. 5. Download Software Purchase FPGA/CPLD Chips/Boards Prepare Required I/O, Such AS LED, LCD, KB… Get Manuals, Examples or Supports Exercise for Several Times Ø Project-Oriented Exercises: 1. Survey the Webs for Interesting Topics 2. Retrieve Corresponding Supports, e. g. , USB from the Phillips Web, MPEG, 8051, ARM, … 3. Study and Design 4. Prototyping HDL T. -C. Huang / NCUE Fall 2005 3

Download Software 1. http: //www. altera. com/support/software/sof-quartus. html 2. Download freeware quartusii_41_sp 2_web_edition_single. exe

Download Software 1. http: //www. altera. com/support/software/sof-quartus. html 2. Download freeware quartusii_41_sp 2_web_edition_single. exe 3. install HDL T. -C. Huang / NCUE Fall 2005 4

Check Your PC’s NIC 1. IPCONFIG /ALL HDL T. -C. Huang / NCUE Fall

Check Your PC’s NIC 1. IPCONFIG /ALL HDL T. -C. Huang / NCUE Fall 2005 5

Licensing 1. https: //mysupport. altera. com/login/signin. asp 2. Sign in required information and save

Licensing 1. https: //mysupport. altera. com/login/signin. asp 2. Sign in required information and save the license. dat from email. HDL T. -C. Huang / NCUE Fall 2005 6

Menu Looks: Migrate from MAX+II HDL T. -C. Huang / NCUE Fall 2005 7

Menu Looks: Migrate from MAX+II HDL T. -C. Huang / NCUE Fall 2005 7

Quartus II Design Flow. tdf (Text Design Files) AHDL, Verilog . bdf (Block Design

Quartus II Design Flow. tdf (Text Design Files) AHDL, Verilog . bdf (Block Design Files) Block Diagram, Graph, Schematics Design Entry Timing Clausure Synthesis Debug Place & Route Timing Analysis Simulation Programming & Configuration HDL T. -C. Huang / NCUE Fall 2005 8

Model. Sim Design Flow Ø Given Libraries DB Ø Developing Libraries (l) 1. 2.

Model. Sim Design Flow Ø Given Libraries DB Ø Developing Libraries (l) 1. 2. 3. 4. 5. Create a new library L; Compile L; Run L; Debug L; Link L to DB as LDB. Ø Project 1. 2. 3. 4. 5. HDL Create a new project P; Add HDL files; Compile HDL with LDB; Run; Debug. T. -C. Huang / NCUE Fall 2005 9

Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu
Hardware Description Language Logic Design using Verilog TsungChuHardware Description Language Logic Design using Verilog TsungChu