Digital Signal Processor 202219 1 Analog to Digital

Digital Signal Processor 2022/1/9 1

Analog to Digital Shift 2022/1/9 2

Digital Signal Processing Applications n n n FAX Phone Personal Computer Medical Instruments DVD player Air conditioner (controller) Digital Camera MP 3 audio Car Navigation Automobile Control And MANY… 2022/1/9 3

What is Analog? , What is Digital? n n n Continuous Signal Similar to Analog watch Processed by Analog Circuit such as OP-amp, RLC circuit n n n Discontinuous Signal The signal is numeric value such as integer or floating point value Processed by Digital Circuit or Digital Signal Processor (Software Programmable) Is Information lost, if we use Digital Signal? 2022/1/9 4

Analog to Digital Conversion [Analog to Digital Conversion ADC] l. Read the value of the wave every sampling period Ts. l. Value is represented in digital bits. Continuous time t [Shannon Sampling Therorem] Analog to Digital Converter Discrete time n l. If, Sampling frequency Fs > 2*Ft (Ft: maximum signal frequency) l. Then, Original Analog wave can be re-covered from the sampled signal l. No information loss Ts = 1/Fs 2022/1/9 5

Why Digital Signal Processing is getting major? n n If we use digital values, Any mathematical computation can be realized by Digital Circuit and/or Digital Signal Processor (computer). In another word, Any innovative mathematical algorithm can be applied to real life by Digital Technology. ¨ n n n This is the reason why I love digital. Analog implementation has many limitations. Such Heavy digital computation can be processed by Semiconductor Devices such as LSI, FPGA, DSPs. Remember OFDM processing (FFT), Such complicated algorithm can only be implemented by Digital Technology. 2022/1/9 6

Digital Signal Processing Applications Most famous: Data compression and de-compression 1. ¨ ¨ ¨ DVD has 133 minutes video data in One-layer. Compression method is MPEG 2 If there is no compression technology, only 35 second video can be stored in DVD one-layer. Digital Filter 2. ¨ 3. 4. 5. 2022/1/9 Remove some components of signal (noise, other frequency) from source signal Noise or Echo cancel Error Correction Modulation and Demodulation for wireless communication 7

But, Human interface is Analog Example: Voice Processing amp ADC DSP DAC amp Data Transmission 2022/1/9 8

System components Amplifier : Analog Signal control 1. n 2. 3. 4. 5. Gain, Noise reduction, Power ADC: Analog to Digital Converter DAC: Digital to Analog Converter DSP: Digital Signal Processor Data Transmission: Data can be Stored in Memory, HDD. SYSTEM NEEDS BOTH ANALOG and DIGITAL device! 2022/1/9 9

TI 6713 DSK CODEC ADC, DAC Voice, Speaker Interface SDRAM 6713 DSP FLASH USB PC-interface 2022/1/9 DIP Switch LED 10

DSK 6416 Block Diagram 2022/1/9 11

TI C 6000 family Architecture XB, PCI, Host Port Internal Memory GPIO Outside Memory EMIF Mc. BSP VCP TCP . M 1. M 2. L 1 . L 2 . S 1. S 2 Register Set B Timers Register Set A EDMA . D 1. D 2 Controller/Decoder PLL DSP CHIP 2022/1/9 12

TI C 6000 family Architecture EMIF 1. ¨ External Memory Interface Connect to outside memory such as SDRAM, Flash Mc. BSP Serial Interface 2. n Connect to Microphone, Speaker thru DAC, ADC GPIO EDMA 3. 4. ¨ ¨ 5. 6. 2022/1/9 General Purpose Interface Enhanced Direct Memory Access Perform data transfer instead of CPU Let CPU work only for computation Timers PLL count time and make interrupt Phase Locked Loop, CLK generation 13

Comparison between MPU and DSP MPU Main Memory Data control ALU Program Data Program DSP Multiply ALU Memory Outside Memory Control n n n 2022/1/9 Memory DSP is strong for Multiply, Higher Memory Bandwidth Parallel Processing Unit for Parallel computation 14

What are the typical DSP algorithms? n The Sum of Products (SOP) is the key element in most DSP algorithms. Multiply and Accumulation (MAC) 2022/1/9 15

Some DSP Parameter TMS 320 C 6211 (@150 MHz) 32 -bit TMS 320 C 6711 (@150 MHz) 32 -bit N/A 64 -bit Extended Arithmetic 40 -bit Performance (peak) 1200 MIPS 1200 MFLOPS 2 (16 x 16 -bit) with 32 -bit result 2 (32 x 32 -bit) with 32 or 64 -bit result 32 32 Internal L 1 program memory cache 32 K Internal L 1 data memory cache 32 K Internal L 2 cache 512 K Arithmetic format Extended floating point Number of hardware multipliers Number of registers 2022/1/9 16

Some DSP Parameter (2) Parameter I/O bandwidth: Serial Ports (number/speed) DMA channels Multiprocessor support Supply voltage Power management On-chip timers (number/width) Cost Package External memory interface controller JTAG 2022/1/9 TMS 320 C 6211 (@150 MHz) 2 x 75 Mbps TMS 320 C 6711 (@150 MHz) 2 x 75 Mbps 16 16 Not inherent 3. 3 V I/O, 1. 8 V Core Yes 2 x 32 -bit US$ 21. 54 256 Pin BGA Yes Yes 17

Interrupts n n 2022/1/9 Interrupts are used to interrupt normal program flow so that the CPU can respond to events. The events can occur at anytime. 18

Normal Computer Operation • Instruction indicated by Program Counter is executed. One Memory PC Current Sequence (Instruction Register) Instruction Control Datapath Read 2022/1/9 Program Read Register File Read ALU Program Data Write 19

Interrupted Operation • By Interrupt signal, PC suddenly indicates Interrupt Service Program One Memory PC Current Sequence (Instruction Register) Instruction Control Datapath Program Read Interrupt Service Register File Read ALU 2022/1/9 Data Write 20

The Need for a DMA n There are two methods for transferring data from one part of the memory to another, these are using: (1)CPU. (2)DMA. n If a DMA is used then the CPU only needs to configure the DMA. Whilst the transfer is taking place the CPU is then free to perform other operations. 2022/1/9 21

Introduction to the EDMA The ‘C 6211/C 6711 on-chip EDMA controller allows data transfers between the level two (L 2) cache memory controller and the device peripherals. n These transfers include: n ¨ Cache servicing. ¨ Non-cacheable memory accesses. ¨ User programmed data transfers. ¨ Host accesses. 2022/1/9 22

EDMA Interface The EDMA allows data transfer to/from any addressable memory spaces. 2022/1/9 23

EDMA Functionality The data transfer is performed with zero overhead. n It is transparent to the CPU which means that the EDMA and CPU operations can be independent. n However, if the EDMA and CPU both try to access the same memory location arbitration will be performed by the program memory controller. n 2022/1/9 24

Audio Thru Example Event triger ADC Memory H/W Interrupt Rcv. Mem Rcv Reg Copy Filter EDMA DAC 2022/1/9 Xmt. Mem Xmt Reg Mc. BSP CPU S/W Interrupt 25

Audio Case CD sampling frequency Fs= 44. 1 KHz n Ts = 22. 6 us n 22. 6 us Time Processing Wait Time EDMA CPU 2022/1/9 26

Some TI DSPs n n n TMS 320 C 64 x: The C 64 x fixed-point DSPs offer the industry's highest level of performance to address the demands of the digital age. At clock rates of up to 1 GHz, C 64 x DSPs can process information at rates up to 8000 MIPS with costs as low as $19. 95. In addition to a high clock rate, C 64 x DSPs can do more work each cycle with built-in extensions. These extensions include new instructions to accelerate performance in key application areas such as digital communications infrastructure and video and image processing. TMS 320 C 62 x: These first-generation fixed-point DSPs represent breakthrough technology that enables new equipments and energizes existing implementations for multi-channel, multi-function applications, such as wireless base stations, remote access servers (RAS), digital subscriber loop (x. DSL) systems, personalized home security systems, advanced imaging/biometrics, industrial scanners, precision instrumentation and multi-channel telephony systems. TMS 320 C 67 x: For designers of high-precision applications, C 67 x floating-point DSPs offer the speed, precision, power savings and dynamic range to meet a wide variety of design needs. These dynamic DSPs are the ideal solution for demanding applications like audio, medical imaging, instrumentation and automotive. 2022/1/9 27