AnalogtoDigital Converters Lecture L 11 2 Verilog Section

Analog-to-Digital Converters Lecture L 11. 2 (Verilog) Section 11. 3

Analog-to-Digital Converters • Converts analog signals to digital signals – 8 -bit: 0 – 255 – 10 -bit: 0 – 1023 – 12 -bit: 0 – 4095 • Successive Approximation

Method of Successive Approximation

Implementing Successive Approximation

ADC 0831 8 -Bit Serial I/O A/D Converter

ADC 0831 Timing

Voltmeter Logic Block Diagram

module binbcd 9(B, P); input [8: 0] B; output [10: 0] P; reg [19: 0] z; integer i; always @(B) begin for(i = 0; i <= 19; i = i+1) z[i] = 0; z[11: 3] = B; for(i = 0; i <= 5; i = i+1) begin if(z[12: 9] > 4) z[12: 9] = z[12: 9] + 3; if(z[16: 13] > 4) z[16: 13] = z[16: 13] + 3; z[19: 1] = z[18: 0]; end P = z[19: 9]; endmodule

Q 3 Q 4 Q 5 Q 6 Q 7 Q 3 (CLK) Q 6 & Q 7 (CS) Data Out (DO) !Q 3 shift (S) [Q 7. . Q 4] == 10 !Q 3 display (D) 7 6 5 4 3 2 1 0 (Capture)

Clock 4. 0 MHz Q 0 2. 0 MHz Q 1 1. 0 MHz Q 2 0. 5 MHz Q 3 0. 25 MHz

4 MHz Clock Xilinx XC 95108 PC 84 CPLD Clock Divider Counter Q 7. . Q 0 Q 3 Q 7 Q 6 CLK CS ADC 0831 Interface DO

Q 3 Q 4 Q 5 Q 6 Q 7 Q 3 (CLK) Q 6 & Q 7 (CS) Data Out (DO) !Q 3 shift (S) [Q 7. . Q 4] == 10 !Q 3 display (D) 7 6 5 4 3 2 1 0 (Capture)

4 MHz Clock Xilinx XC 95108 PC 84 CPLD Clock Divider Counter Q 7. . Q 0 Q 3 Q 7 Q 6 Count Detect Logic (Q 7. . Q 4 = 10102) Capture CS ADC 0831 Interface Q 3 Shift Register S 7. . S 0 Load CLK Display Register D 7. . D 0 !Q 3 Clock Data Clock DO

Simulation of adconv

Xilinx XC 95108 PC 84 CPLD (Shift Register S 7. . S 0) (!Q 3) (Capture) Load Display Register D 7. . D 0 Clock 0 Binary-to-BCD Converter Hundreds 1 Tens Units 0 7 -Segment Decoder 7 7 a. . g dpt a. . g Voltage Display