Verilog XL Tutorial By Greg Edmiston Scott Mc

Verilog XL Tutorial By Greg Edmiston Scott Mc. Clure August 2004

Tutorial Disclaimer n This tutorial includes one way of simulating in Verilog XL. This is not necessarily the best way of simulating, depending on your requirements. This tutorial is a simple step -through designed to familiarize the user with Verilog XL, and thus is basic in nature. More advance simulations are not found in this tutorial.

Create Verilog File n n Create a text file with the text shown here This code represents a basic circuit with delay and test stimulus Save as “example. v” Verilog code files often have a “. v” file extension

Enter ICFB n Type “who am i” ¨ Gives n n xhost address setenv DISPLAY {xhost} Type “icfb &” to start Cadence

Import Verilog File in ICFB n Import the “example. v” Verilog file by choosing File >> Import >> Verilog in ICFB CIW

Importing Verilog File n n n “Verilog In” window pops up Set Target Library Name to “new” Highlight “example. v” in file selection box at the top of the window Press the Add button on the “Verilog Files to Import” line Click OK at the top of the “Verilog In” window

Verify File Import n Open up the Library Manger from the CIW and inspect to ensure the “new” library includes a cell named “circuit_with_delay”

Verify File Import n Open the Schematic view of the “circuit_with_ delay” from the Library Manager and verify that it resembles the screenshot to the left

Running Verilog XL n n Close all windows except a terminal From your home directory type “verilog +gui example. v” n n Verilog should open with your example loaded Note: “example. v” has to be saved in your home directory for this command to function

Simulating with Verilog XL Verilog should open the Sim. Vision Design Browser and Console n The stimcrct module should be displayed under the simulator icon n

Simulating with Verilog XL Click on the stimcrct icon n The circuit inputs and outputs should now be visible under Signal/Variable n

Simulating with Verilog n With the stimcrct highlighted choose Select>>Signals

Simulating with Verilog XL n Now that the signals are highlighted, send them to the logic display by clicking on the indicated button Click Here

Simulating with Verilog XL n Run Button Click the Play button to run the simulation

Simulating with Verilog XL n Since the simulation has no initial stop point the output will appear similar to the window to the left

Simulating with Verilog XL n n To rerun the simulation it must first be reset Reset the simulation by choosing “Reinvoke Simulator” from the simulation menu

Simulation with Verilog XL n Run Button Run the simulation by pressing the Run button

Simulation with Verilog XL n Simulation output should look like this

Conclusion This concludes the Verilog XL Tutorial n This tutorial was derived from the SMU Cadence Verilog XL Tutorial n http: //engr. smu. edu/~mitch/class/3381/veri log_intro. pdf n