Amplification ID Rd ID Vds ID Slope Vgs
- Slides: 17
Amplification ID Rd ID Vds ID Slope Vgs Q point Large Rd Q point Vgs © Bob York Small Rd Vds
Power Dissipation ID Rd Imax ID Vds Vgs Vmax © Bob York Vds
CD 4007 * CD 4007 NMOS and PMOS transistor SPICE models * Typical - Typical Condition . model Mbreak. ND NMOS + Level=1 Gamma= 0 Xj=0 + Tox=1200 n Phi=. 6 Rs=0 Kp=111 u Vto=2. 0 Lambda=0. 01 + Rd=0 Cbd=2. 0 p Cbs=2. 0 p Pb=. 8 Cgso=0. 1 p + Cgdo=0. 1 p Is=16. 64 p N=1 *The default W and L is 30 and 10 um respectively and AD and AS *should not be included. . model Mbreak. PD PMOS + Level=1 Gamma= 0 Xj=0 + Tox=1200 n Phi=. 6 Rs=0 Kp=55 u Vto=-1. 5 Lambda=0. 04 + Rd=0 Cbd=4. 0 p Cbs=4. 0 p Pb=. 8 Cgso=0. 2 p + Cgdo=0. 2 p Is=16. 64 p N=1 *The default W and L is 60 and 10 um respectively and AD and AS *should not be included. © Bob York
2 N 7000 From Data. Sheet: (~2. 5 um technology) *2 N 7000 SPICE MODEL *. MODEL 2 N 7000 NMOS (LEVEL=3 RS=0. 205 NSUB=1. 0 E 15 +DELTA=0. 1 KAPPA=0. 0506 TPG=1 CGDO=3. 1716 E-9 +RD=0. 239 VTO=1. 000 VMAX=1. 0 E 7 ETA=0. 0223089 +NFS=6. 6 E 10 TOX=1. 0 E-7 LD=1. 698 E-9 UO=862. 425 +XJ=6. 4666 E-7 THETA=1. 0 E-5 CGSO=9. 09 E-9 L=2. 5 E-6 +W=0. 8 E-2). ENDS * For large currents, Id-Vgs is approximately linear (dotted line) For small currents (<100 m. A) the behavior is parabolic © Bob York
2 N 7000 Subthreshold currents © Bob York
2 N 7000 Pdiss=400 m. W © Bob York
Measuring Parameters gm, Vt This is a simple method for estimating device parameters Vdd • Use diode-connected device (forces operation in saturation) • With an ammeter, vary the supply voltage until the desired bias current is achieved, and record the gate voltage Vgs • Adjust Vdd so that Vgs changes by a small amount (say 50 m. V), and record the resulting change in current • Continue varying the gate voltage until the current increases by a factor of 4. If the device follows a parabolic law, this means that the (Vgs-Vt) must have changed by a factor of 2 For r = 2: © Bob York A Vout
Common Source Amps Vdd Rg 1 Vdd Rd ∞ ∞ Rd Rg 1 Rgen Vout Vin ∞ ∞ Vout RL Vgen Rg 2 Rgen Vin Rin © Bob York vin gmvin Rout Vgen Rin vin gmvin Rout RL
Lab Circuits +10 V 220 Ω 100 kΩ Vin 100 kΩ 220 Ω 10 μF Vout Vin 10 μF 10 kΩ Rg 1 Vout Rg 1 100 Ω 10 μF © Bob York
Common Source Amplifier Vdd Rg 1 Rsig Rd ∞ ∞ Vout RL Vsig Rg 2 Rs © Bob York ∞
Common Gate Amplifier Vdd Rd ∞ ∞ G Vout D gmvgs 1/gm S D 1/gm gmvin ∞ S Vin Id Vin © Bob York 1/gm vin gmvin Rd Vout G
Common-Gate Amplifier Vdd Rg 1 Rg 2 Rd ∞ Vout ∞ Rgen RL ∞ Vgen Rs Rgen Vgen © Bob York Rin vin gmvin Rout RL
Lab experiment +10 V 220 Ω 10 μF Rg 1 10 μF 100 kΩ 10 kΩ Vin Rs 100 μF © Bob York Vout 100 Ω
Source Follower Vdd Rg 1 Rgen Rd ∞ ∞ Vout Vgen Rg 2 Rs RL © Bob York
CS Resistive Feedback Rf Vdd Rd Id Rf ∞ Vout ∞ ∞ Vin © Bob York RL Vin Rg Vin ∞ Vout vgs Rgen gmvgs Rout Vgen Rg vgs gmvin RL
CD 4007 VDD 1 14 P P 2 13 3 12 4 P 11 N 5 VSS © Bob York 2 13 1 6 3 11 10 8 5 7 4 12 10 6 7 14 N N 9 8 9
Active Loading Vdd Q 2 Q 3 C 2 Rf C 1 Q 4 Q 1 Vin © Bob York Vout RL
