A RequirementsDriven PLD Design Flow MAPLD 2009 Dominic

A Requirements-Driven PLD Design Flow MAPLD 2009 Dominic Lucido Sr. Applications Engr

Mentor Offers Complete Electrical Systems Design Automation PCB Design EWIS Design • Boardstation • Expedition • Data Management FPGA/ASIC Design • Capital Harness System • Questa adv verification • HDL Designer • Precision synthesis • Test. Kompress DFT • Model. Sim simulator • Calibre phys verification • Formal. Pro Electro-Mechanical System Simulation • System. Vision Fire Control Embedded SW • Nucleus Secure Kernel

Requirements Driven Development Process n . . . is needed by many Safety Critical & Mission Critical Industries: — — — Commercial Aviation Military Space Medical Electronics Automotive Railway Robotics Industrial Controls Banking Systems Cruise Ships Shipping

DO-254 in the Aircraft Certification Process FPGA/ASIC • Built to DO-254 standards as reviewed by DER Timeline ~2 years

Review: Principles of DO-254 n DO-254 Lifecycle Planning DO-254 Lifecycle Requirements Capture Conceptual Design Detailed Design PHAC n DO-254 Key Concepts Detailed planning captured in PHAC — Requirements driven flow — n Thorough verification — Flow under strict CM — Audits against PHAC — n Implementation n Production Transition Requirements tracing — Internal QA reviews External SOI audits Proof of compliance shown through artifacts 5

DO-254 Principles Move to Higher Levels End-Product (System) Customer System Design & Analysis DO-254 Board Design & Analysis DO-254 Requirements Management & Tracing Chip Design & Analysis 6

Managing the Design and Virtual Prototyping Process Enterprise Requirements Database Advanced Requirements Tracing Engine Requirements Definition Functional Design Requirements Verification Functional Verification Architecture Validation/Test Architecture Design System Integration/Test Component Design Component Test Design IP Verification IP IP

Overall Objective n Produce a traceable “Verified Implementation” — Requirements Coverage n — Functional Coverage n — Demonstrate that all the requirements have been implemented. Demonstrate that the required design functionality has been fully tested Change Tracking and Control n Track requirements changes and manage their impact throughout the development process.

Tracing Requirements into FPGA/ASIC Design Verilog VHDL n RTL Code — n Verification Plan — Verilog VHDL n UCDB Associate HDL testbench constructs and coverage items with verification requirements Verification Results — Log Files Associate verification requirements with design requirements Testbench Code — n Associate HDL design constructs with design requirements Associate verification results, such as text logs and coverage databases, with verification requirements.

The Challenge: Tracing Requirements down into the Implementation and Verification Details Wide variety of data to track: n System Level Requirements (DOORs) n Subsystem Specification (Word) n Design Source (VHDL) n Test Plan (Excel) n Testbench (System. Verilog) n Simulation Verification Results (UCDB & text logs) n Hardware Test Results (Instrument &ATE logs)

Tracing Requirements into FPGA/ASIC Design

Tracing Requirements into PCB Design n Schematic — n Constraints — n n Associate constraints on a net with a requirement Layout — Log Files Associate a schematic block with a requirement Associate an area of a layout with a requirement Verification Results — Associate results from PCB verfication tools such as signal integrity, manufacturability and thermal analysis with a requirement

Tracing Requirements into PCB Design

Tracing Requirements into ESL Design UML / C++ n C / C++/ Sys. C n TLM / Sys. C n Functional Model — Architectural Model / Virtual Prototype — Log Files Associate requirements with an architectural level model TLM Model — n Associate requirements with a system level functional model Associate requirements with a TLM model Model Verification Results — Associate requirements with results from all levels of model simulations

Tracing Requirements into ESL Design

Tracing Requirements into EWIS Design n Design — n CHS Constraints — n n Associate requirements with EWIS constraint definitions FMEA Results — Log Files Associate requirements with EWIS design elements Associate requirements with results of Failure Modes and Effects analysis EWIS Verification Results — Associate requirements with simulation results for DC, transient sneak path and switch state analysis

Tracing Requirements into EWIS Design

Requirements Driven Development Process n n Customer Level System Level n Subsystem Level n Module/LRU Level n ASIC/FPGA Level 18 FPGA Assurance Workshop, Feb 2009 ESL Flow EWIS Flow PCB Flow ASIC/FPGA Flow

Requirements Volatility n Definition — n A measure of the number of new, deleted and changed requirements relative to the total number of requirements Impact System Quality — Development Schedules — n Measurement Can be Difficult (An automated tool really helps!) — Powerful project management tool — 19

Requirements Tracing with Req. Tracer Verilog VHDL C / C++ Matlab™ Design and Testbench Source Files & PCB Design Data Requirements-aware Access to Test Result Data Enterprise Level Requirements Databases Req. Tracer Text Log Files Requirements Documents &Text Files 20 ASCII Test Results UCDB Simulation Results Change Impact and Traceability Analysis Automated Traceability Report Generation

Tag n n TAG TAG TAG Configure Req. Tracer to capture existing requirements Tag new requirements REQ_001 REQ_002 REQ_003 REQ_004 REQ_005 Design Specification

Trace TS EMEN L P M I COVERS IMPL EME NTS CO VER S IMPL EEMMEENTS L P IM COVERS Hardware Requirements 40% Design Specification Can you prove all requirements are implemented and tested? Certification Authority 60% RTL Design What shall I work on next? Hardware Designers What is this code for? System Architect

Monitor/Analyze CHANGE COVERS TS EMEN L P M I IMPACT IMPL EME NTS CO VER S IMPACT IMPL EEMMEENTS L P IM COVERS Hardware Requirements 20% Design Specification System Architect Project Manager IMPACT RTL Design 40% 60% Which tests need updating now the design has changed? Can we make a change and still release on time? How risky would it be if I changed this? IMPACT Quality Manager

Basic vs. Advanced Requirements Tracing n Basic — — — DOORS Support Word/Excel Support Design Artifact Import External Filename Ref Traceability Report CM Mechanism n Advanced — — — DOORS Interface Word/Excel Interface Text File Interface Design Data Interfaces Data Environment Link Design Tool Interfaces Requirements Aware Change Tracking Traceability Report Library Programmable Report Generator IP-Safe Interactive Tracing Report

Advanced Requirements Tracing n Advanced — — — DOORS Interface Word/Excel Interface Test File Interface Design Data Interfaces Data Environment Link Design Tool Interfaces Requirements Aware Change Tracking Traceability Report Library Programmable Report Generator IP-Safe Interactive Tracing Report

Traceability Across Design Domains Advanced Requirements Tracing Engine Enterprise Requirements Database EE ME Electrical Design Mechanical Design 26 WCR, IESF Seattle, May 2009 IP SW Software Design

Traceability across the Supply Chain In-House Enterprise Requirements Database S W M E EE Advanced Requirements Tracing Engine Supplier A EE SW ME IP Supplier B EE 27 WCR, IESF Seattle, May 2009 ME SW

Req. Tracer™ Managing Requirements throughout your Design Flows Requirements Capture & Tracing Analysis & Reporting Change Management Link Automated Reports, Specs, Design & Results Impact Analysis to Control Schedules XML ASCII Trace Through Deign Implementation & Testing 28

29 Presenter Initials, IESF Seattle, May 2009