Design Flow Design Specification Design Entry Schematic Design
- Slides: 7
Design Flow Design Specification ¡ Design Entry ¡ ¡ Schematic Design VHDL Verilog HDL Function Verification Delta Delay를 적용하여 입력된 Test Waveform(Test Bench Timing file)을 이용) Timing Verification Device Delay를 적용하여 입력된 Test Waveform(Test Bench Timing file)을 이용) Design Modification Device Programming In-System Verification System Production
Design Software Project 선언 Main menu file New Project Wizard(5단계로 이루어짐) 1. (page 1 of 5) Entity 입력시 Top-Level의 Entity 이름과 같게… 2. (page 3 of 5) 디바이스 선택(EP 2 C 35 F 672) Design Entry Main menu file New ¡ Block Diagram/Schematic file ¡ VHDL ¡ Verilog HDL Compile Main menu Processing Start Compilation Assignment (Device) Main menu Assignments Device : Device 선택(EP 2 C 35 F 672) Assignment (Pin) Main menu Assignments Assignment Editor : Pin 선택 Function Simulation Main menu file New Vector Waveform File Main menu Processing Start Simulation
실습(ex 1 -4) 입 력 출 력 A 1 A 2 B 1 B 0 0 1 0 1 0 1 1 1 1 1 C 1 S 0 C 0
