8085 Microprocessor S Senthil Kumar Dept of Aero

  • Slides: 25
Download presentation
8085 Microprocessor S. Senthil Kumar, Dept. of Aero, KCT

8085 Microprocessor S. Senthil Kumar, Dept. of Aero, KCT

8085 A Pin diagram and Signals

8085 A Pin diagram and Signals

8085 Architecture

8085 Architecture

8085 Programmable Registers

8085 Programmable Registers

8085 Bus Structure

8085 Bus Structure

8085 Microcomputer based Memory

8085 Microcomputer based Memory

8085 Microcomputer based Memory

8085 Microcomputer based Memory

Memory – 4 x 4 -bit Register (single chip)

Memory – 4 x 4 -bit Register (single chip)

Memory – 4 x 8 -bit Register (one chip and two chips)

Memory – 4 x 8 -bit Register (one chip and two chips)

Memory – 4 x 4 -bit Register (two chips and chip select)

Memory – 4 x 4 -bit Register (two chips and chip select)

Memory – 4 x 4 -bit Register (two chips and 4 address lines)

Memory – 4 x 4 -bit Register (two chips and 4 address lines)

R/W Memory model and ROM model (Memory Chip)

R/W Memory model and ROM model (Memory Chip)

Memory chip with 256 registers (256 bytes of memory)

Memory chip with 256 registers (256 bytes of memory)

Memory Map Ø The memory map is a picture representation of the address range

Memory Map Ø The memory map is a picture representation of the address range and shows where the different memory chips are located within the address range.

Generation of Control Signals for Memory and I/O

Generation of Control Signals for Memory and I/O

Functions performed by 8085 Ø Microprocessor-initiated operations • Memory Read: Reads data (or instructions)

Functions performed by 8085 Ø Microprocessor-initiated operations • Memory Read: Reads data (or instructions) from memory • Memory Write: Writes data (or instructions) into memory • I/O Read: Accepts data from input devices • I/O Write: Sends data to output devices Ø Internal operations • Store 8 -bit data • Perform arithmetic and logical operations • Test for conditions • Sequence the execution of instructions • Store data temporarily during execution in the defined R/W memory locations called stack Ø Peripheral (or externally initiated) operations • Reset, Interrupt, Ready, Hold

Instruction Cycle, Machine Cycle and T-State

Instruction Cycle, Machine Cycle and T-State

8085 Instruction Fetch operation (Opcode Fetch – 4 T-states)

8085 Instruction Fetch operation (Opcode Fetch – 4 T-states)

Opcode Fetch (4 T-states) – Timing Diagram

Opcode Fetch (4 T-states) – Timing Diagram

8085 – Demultiplexing the Bus AD 7 -AD 0

8085 – Demultiplexing the Bus AD 7 -AD 0

8085 Memory Read operation

8085 Memory Read operation

Memory Read machine cycle – Timing Diagram

Memory Read machine cycle – Timing Diagram

Memory Write machine cycle – Timing Diagram

Memory Write machine cycle – Timing Diagram

I/O Read machine cycle – Timing Diagram

I/O Read machine cycle – Timing Diagram

I/O Write machine cycle – Timing Diagram

I/O Write machine cycle – Timing Diagram