8085 Microprocessor Architecture 1 8085 CPU Block Diagram

8085 Microprocessor Architecture 1

8085 CPU Block Diagram 2

The 8085 Block Diagram n Registers – hold temporary data. n n Instruction register (IR)– holds the currently executing instruction. Instruction Decoder (ID)- decodes the instruction. Once decoded, the instruction controls the remainder of the MPU, memory and IO through the timing and control block. 3

The 8085 Block Diagram n n Temporary register- holds information from the memory or register array. An input of the ALU. Increment/Decrement address latch – It adds or subtracts one from any of other registers in register array. Why are the PC and SP registers are 16 -bit ? 4

Signals and I/O Pins 5

Intel 8085 Pin Configuration 6

Clock Pins n n 8085 MPU has 3 pins that control or present the clock signal. n X 1 and X 2 pins determine the clock frequency. n CLK OUT is a TTL square-wave output clock. 8085 A X 1 CLK OUT 6 MHz X 2 The CLOCK OUT is one-half the crystal frequency. 7

8085 Pinout n n 8085 μp consists of 16 signal pins use as address bus. Divide into 2 part: A 15 – A 8 (upper) and AD 7 – AD 0 (lower). n A 15 – A 8 : Unidirectional, known as ‘high order address’. n AD 7 – AD 0 : bidirectional and dual purpose (address and data placed once at a time). n AD 7 – AD 0 also known as ‘low order address’. n To execute an instruction, at early stage AD 7 – AD 0 uses as address bus and alternately as data bus for the next cycle. n The method to change from address bus to data bus known as ‘bus multiplexing’. 8

8085 Pinout n Group of signals consists of : n n n Two control signals (‘RD’ – read; and ‘WR’ write). Three status signals (IO/M, S 1, and S 0) to recognize nature of operation. ALE (Address Latch Enable) signal : n active high signal - generated to show the start of 8085 operation. n When transition 1 -to-0: indicate that lines AD 7 -AD 0 (AD 7 -AD 0 = A 7 -A 0) act as address lines. 9

ALE used to demultiplex address/data bus 10

Control and Status Signals n Signals: n n n RD – Read (active low). To indicate that the I/O or memory selected is to be read and data are available on the bus. WR – Write: Active low. This is to indicate that the data available on the bus are to be written to memory or I/O ports. IO/M – To differentiate I/O operation of memory operations. n ‘ 0’ - indicates a memory operation. n ‘ 1’-indicates an I/O operation. IO/M combined with RD and WR to generate I/O and memory control signals. S 1 dan S 0: Status signals, similar to IO/M, can identify various operations as shown on the following table : 11

Control and Status Signals. 12

Interrupt Signals n 8085 μp has several interrupt signals as shown in the following table. 13

Interrupt signals n n An interrupt is a hardware-initiated subroutine CALL. When interrupt pin is activated, an ISR will be called, interrupting the program that is currently executing. Pin Subroutine Location TRAP 0024 RST 5. 5 002 C RST 6. 5 0034 RST 7. 5 003 C INTR * Note: * the address of the ISR is determined by the external hardware. 14

Interrupt signals n n INTR input is enabled when EI instruction is executed. The status of the RST 7. 5, RST 6. 5 and RST 5. 5 pins are determined by both EI instruction and the condition of the mask bits in the interrupt mask register. 15

Interrupt Vectors 16

A circuit that causes an RST 4 instruction (E 7) to be executed in response to INTR. n n When INTR is asserted, 8085 response with INTA pulse. During INTA pulse, 8085 expect to see an instruction applied to its data bus. 17

RESET signal n Following are the two kind of RESET signals: n n RESET IN: an active low input signal, Program Counter (PC) will be set to 0 and thus MPU will reset. RESET OUT: an output reset signal to indicate that the μp was reset (i. e. RESET IN=0). It also used to reset external devices. 18

RESET signal 19

Direct Memory Access (DMA) n n DMA is an IO technique where external IO device requests the use of the MPU buses. Allows external IO devices to gain high speed access to the memory. n n Example of IO devices that use DMA: disk memory system. HOLD and HLDA are used for DMA. If HOLD=1, 8085 will place it address, data and control pins at their high-impedance. A DMA acknowledgement is signaled by HLDA=1. 20

MPU Communication and Bus Timing Figure 3: Moving data form memory to MPU using instruction MOV C, A (code machine 4 FH = 0100 1111) 21

MPU Communication and Bus Timing n The Fetch Execute Sequence : 1. The μp placed a 16 bit memory address from PC (program counter) to address bus. – Figure 4: at T 1 – – – 2. The high order address, 20 H, is placed at A 15 – A 8. the low order address, 05 H, is placed at AD 7 - AD 0 and ALE is active high. Synchronously the IO/M is in active low condition to show it is a memory operation. At T 2 the active low control signal, RD, is activated so as to activate read operation; it is to indicate that the MPU is in fetch mode operation. 22

MPU Communication and Bus Timing Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A. 23

MPU Communication and Bus Timing 3. 4. T 3: The active low RD signal enabled the byte instruction, 4 FH, to be placed on AD 7 – AD 0 and transferred to the MPU. While RD high, the data bus will be in high impedance mode. T 4: The machine code, 4 FH, will then be decoded in instruction decoder. The content of accumulator (A) will then copied into C register at time state, T 4. 24