TK 2633 8085 Microprocessor Architecture Demultiplexing the AD

TK 2633 8085 Microprocessor Architecture – Demultiplexing the AD 7 -AD 0 DR MASRI AYOB

Bus Demultiplexer AD 7 -AD 0 • It is necessary to have the knowledge and skills to demultiplex data bus and address bus as it is important in hardware design applications. • Like previous example (referring to timing diagram): MOV C, A => with machine code (4 FH) 2

Bus Demultiplexer AD 7 -AD 0 Figure 1 3

Bus Demultiplexer AD 7 -AD 0 • From fig 1, to run instruction MOV C, A the high order address bus maintained as bus address for three clock periods. • However the low order address bus (05 H) was eliminated after first time state. • The address need to be latched as to identify memory address. • After T 1, the bus AD 7 -AD 0 now becomes 4 FH. 4

• Schematic diagram to latch low order address bus. 05 H Figure 2 5

Bus Demultiplexer AD 7 -AD 0 • In Fig 2, the AD 7 -AD 0 bus is connected to the input of latch buffer 74 LS 373. • The ALE signal is connected to enable pin (G) at latch, and the output control signal is grounded (OC). • When the ALE signal is active high, the latch will act according to the input instruction (the output changes according to input data). • At T 1 the latch output value is 05 H, and when ALE is low, the byte data 05 H is hold until the new next ALE signal activated. • This causes the output latch is low order address memory A 7 -A 0 (05 H). 6

Control Signals • It is necessary to generate two RD control signals, one for memory and one for peripheral. • Similar to WR control signal; one for writing to memory and one for writing to output peripheral. 7

Control Signals Figure 3: Example of schematic diagram to generate control signals. 8

Control Signals and Demultiplexing Figure 4: the combination of control signals as well as demultiplexing the bus system. 9

Thank you Q&A 10