SERENA Project the kick off SERENA Progress SERENA

SERENA Project: the kick off SERENA Progress

SERENA Current schedule SERENA Progress

SERENA LONG TERM PLAN SERENA Progress

SERENA DOCUMENTATION (see Released_doc annex) SERENA Progress

SERENA SYSTEM AIV (see AIV_program_0. 3 annex) SERENA Progress

SERENA SCU / SYSTEM Outlook • I/Fs developing status • DHSU Architecture • System Budgets SERENA Progress

SERENA SCU / SYSTEM NPA-IS System PICAM 90°x 360° Main S/C Power Bus +28 VDC Redu S/C Power Bus +28 VDC SCU Limited PWR Bus 28 VDC Unit 2 S p. W 10 / (50) LVDS Link S/C OBDH S/C Spacewire SERENA Bus Redu Sp. W Bus SCU L. PWR +28 VDC NPA-IS SCU Electronics Unit- 1 (ELENA box) box Mb/s ELENA / MIPA 1. 8° x 76°/ 9°x 180° Unit 3/4 2 Mb/s RS-422 Link SCU Limited Power Bus 28 VDC Unit 5 STROFIO 20° FOV S/C fixation platforms SERENA Progress

SERENA SCU / SYSTEM I/Fs SERENA Progress

DHSU Block Diagram Developing & Testing I/F 50 MHz OSC Loc. TM/Loc. TC Serial 2 Mb/s I/F Drivers Transceiver 3 -Cube Power Switch ELENA I/F Compressor MIPA I/F 2 -EEPROM 128 kx 8 with EDAC Transceiver 3 -EEPROM Power Switch Leon-3 FT core courtesy By Gaisler Research TM [A 0. . A 16] 2 -SRAM 512 kx 8 with EDAC EMC FILTER SURV PROM 8 kx 16 3 -SRAM 512 kx 8 with EDAC +3. 3 V DC / DC Converter S/C POWER I/F EMC FILTER Loc. TM/Loc. TC Serial Sp. W I/F Drivers ACTEL RTAX 2000 S SPACEWIRE kernel ECSS-E-50 -12 A TM/TC LVDS Transceivers S/C SPACEWIRE TC/TM I/F POWER Control I/F PWR EN/DIS LINEs 1 -SRAM 512 kx 8 with EDAC Loc. TM/Loc. TC Serial 2 Mb/s I/F Drivers STROFIO I/F PICAM I/F EDAC 2 x 12 to 16 Reconstructor [D 0. . D 24] Loc. TM/Loc. TC Serial 2 Mb/s I/F Drivers Reset Circuitry BP-MPO DHSU DPU, AMD - V 1. 0 Rev. C SERENA Progress

SERENA I/Fs architecture LEON CORE AHB Interface AHB Controller AMBA AHB Memory Controller Timers Irq. Ctrl AHB/APB Bridge UARTs I/O Ports AMBA APB To COMPR I/F To SRAM I/F TO EEPROM I/F APB/Switch Bridge CFG Port ELE Ser IF MIP Ser IF STR Ser IF PIC Sp. W IF Main S/C Sp. W IF Redu S/C Sp. W IF Legend: 2 Mb/s I/F SCU Sp. W I/F SERENA Progress

SERENA Grounding scheme SERENA Progress

DATA HANDLING: Main DPUs inheritance FORMER AMDL’s related experiences: • CLUSTER CIS-2: DPU Designing & On-Board S/W (MAS 281) • DARA-NASA EQUATOR-S ESIC: On-Board S/W (MAS 281) • DMARS-96 &ESA MARS EXPRESS PFS: FFT DPU Design & On. Board S/W (AD 21000) • DOUBLE STAR HIA: Composition Experiment On. Board S/W (MAS 281) • ESA SMART-1 AMIE: Microcamera - Power supply & S/C I/F board • NASA/JPL DAWN: VIR On board compression S/W & GSE CURRENT AMDL’s related experiences: ESA BEPICOLOMBO SERENA: PM and Design Manager ESA EXOMARS IRAS: Electronics Design Manager 03 -Nov-2005 AMDL - SERENA Progress R-1 SERENA Progress

DHSU Developing SCU H/W demonstration mdel Full representative. SCU board 100% mastered SERENA Progress

SERENA ELE/SCU CPPA SERENA Progress

SCU SENSORS I/Fs: MIPA #1/2 SERENA Progress

SCU SENSORS I/Fs: MIPA #2/2 SERENA Progress

SCU SENSORS I/Fs: ELE-STROFIO #1/2 SERENA Progress

SCU SENSORS I/Fs: ELE-STROFIO #2/2 SERENA Progress

SENSORS I/F implementation: e. g. MIPA SERENA Progress

Sp. W Testing Configuration SCU SIM: PENDER’s GR-XC 3 S 1500 FPGA based LEON 3 PICAM & S/C SIM I/F & HOST USB I/F LVDS I/F SERENA Progress

DHSU description The DHSU unit consists of the following functional blocks housed on a 100 x 160 mm 2 Eurocard board: - Hi Rel FPGA based Control Unit ( Leon 3 FT) -Hi Rel SRAM 512 x 2 k. B EDAC Protected - HI Rel local power converter and power distribution switches - Rad Tolerant EEPROM 128 x 2 k. B EDAC Protected Optionally on a second 100 x 100 mm 2 mezzanine board: - Rad Tolerant 200 MIPS DSP Based DPU Compressor and glue logic Main DHSU tasks are: - To receive and to distribute command to Sub-sys - to acquire data from active Sub-Sys - to download science and H/K data through the S/C interface ; - to control and manages the IRAS suite functions - to control and distributes primary power to Sub-Sys SERENA Progress

EDAC Faulty Case: corrupted bus: - Above: 1 err detected & recovered - Bottom: 2 err detected SERENA Progress

DHSU: LEON 3 H/W STATUS: • Updating developing configuration of PENDER’s GR-XC 3 S-1500 FPGA based LEON 3 development/prototyping board XCONFIG & XGRLIB and uploading procedures via IMPACT tool (Xilinx) tested and running for customized Leon 3 configuration. For ACTEL developing procured A 3 PE 3000 complete developing platform • Boot PROMs prepared. • Received directly from Gaisler a customized. MCS version which encloses the optional GR Sp. W core. S/W STATUS: • Updating S/W Development tools GRMON, GRSIM, BCC, GDB/DDD integrated on Cygwin and Win XP platforms. S/W development controlled under ECLIPSE 3. 2. DOC Status Preliminary definition of the internal I/Fs to Sub-Subsystem communication protocol issued. Provided a 2 nd issue of Communication Interface Control Document BC-SRN-0045 -00 -01_. Doc OPEN ISSUES: • no major issues SERENA Progress

BUDGETS Mass Power TM BUDGETS Ref BC-EST-RS-02522 Draft 2 TC Budget refined according to BC-SRN-0045 -00 -01 Communication Interface Control Document SERENA Progress