Previously l l Fetch execute cycle Pipelining and

Previously l l Fetch execute cycle Pipelining and others forms of parallelism Basic architecture This week we going to consider further some of the principles of a modern processor.

Principles for Modern Processor l. Outcomes: At the end of this session, you should be able to – – Describe the basic principles of modern processors Explain how hardware decisions having an effect on CPU design. Introduce the concept of interpreters. Introduce CISC and RISC.

History 1 l l l Late 1950 s, IBM recognised supporting a single family of machines, using the same set of instructions had advantages for both IBM and it's customers. Many computers, with different implementation could be produced, but all could execute the same program, differing only in speed and price. A way was needed to enable the lower cost machines to execute the same instructions as high-performance expensive machine. Interpreters were the answer.

l l l Instead of developing a different hardware CPU consisting of a whole bunch of electronics, a program can be used that do these operations (fetching, decoding, and executing instructions). Simulating the new processor. This is an interpreter.

l l l Enables backward compatibility and compatibility across a range of processors. Machines the interpreter runs on can be simpler and less expensive than a hardware processor for the target machine. This potentially can lead to significant savings if target machine has a large set of complicated instructions.

Complex instructions l l Early computers had small, simple instructions. Computers that are more powerful were wanted, so more powerful and complicated instructions were needed. Complex instructions often lead to faster program execution, but the time taken to perform an instruction may take longer. Complex instructions were also better because the execution of individual operations could be overlapped, or otherwise executed in parallel.

l A common processor in the 80 s the Motorola 68000 had a large interpreted instruction set. Fast read-only memory (control stores) that could hold interpreters was another factor in success of interpreter-based approaches. The access speed of these was getting close to that of directly executed execution times.

l During the 70 s and early 80 s, some groups went against the trend and design CPUs that were not interpreted. No need for backward compatibility, the designers were less restricted and choose new instruction sets to maximise performance. Initial emphasis was on simple instructions that executed quickly. Later that instructions that could be started quickly was another key to improving performance.

l Initially these processors were designed with a smaller number of instructions around 50, so name Reduced Instruction set computer (RISC) in contrast with Complex instruction set Computer (CISC) (VAX, etc). Later RISC processors may have larger set of instructions.

Why has RISC not replaced CISC completely? l l l Backward compatibility, billons pounds (or dollars) have been invested in software for the Intel line Intel employed some of the RISC ideas in the 486 s upwards. It contained a RISC core to execute simplest and most common instructions, while the more complicated instructions in the usual CISC way. So common instructions are generally fast and less common instructions are slow. hybrid approach not a pure RISC design. This allows higher performance but still allowing old software to run unmodified.

General Principles for Hardware Design l External constraints such as requirement of being backward compatible (able to use older processor instruction sets) with existing architecture require compromise from time-totime, but for there are some principles that designers aspire to meet.

Tannebaum, 2006 l l l All instructions are directly executed by hardware Maximise rate at which instructions are issued Instructions should be easy to decode Only load and stores should reference memory Plenty of registers

All instructions are directly executed by hardware (Tannebaum, 2006): l All common instructions are directly executed by the hardware, eliminating the interpretation provides higher speed for instructions. CISC (Complex Instruction Sets) instruction sets, complex instructions are broken down into simpler instructions, extra steps slow down, if these instructions are not frequently used it may be acceptable

Maximise rate at which instructions are issued(Tannebaum, 2006): Parallelism is a powerful way to improve performance by using multiple instructions executed at once.

Instructions should be easy to decode (Tannebaum, 2006): l A limit on the rate of instructions decode is determine by what resources are needed. Making instructions regular, fixed length, and having small number of fields, are methods that can aid this process.

Only load and stores should reference memory (Tannebaum, 2006): : l l Using main memory is slower than registers. Operations of moving memory to register can be performed in separate instructions. Only the load and store instructions should reference memory.

Plenty of registers (Tannebaum, 2006): l Accessing memory is slow, so many registers (over 32) may be needed, and so once data is fetched, it can be kept in a register until it is no longer needed. Running out of registers, and having to send data into memory, only to reload them is undesirable and should be avoided as much as possible. An adequate number of registers are needed.

References and further reading l Tannebaum AS(2006) Structured Computer Organisation pg 59 -62, ISBN 0 -13 -148521 -0