The Fetch Decode Execute Cycle The History of

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The Fetch Decode Execute Cycle The History of Computing © London Grid for Learning

The Fetch Decode Execute Cycle The History of Computing © London Grid for Learning www. HOC. lgfl. net

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Fetch Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Decode Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History

The Fetch, Decode, Execute Cycle Execute Processor (CPU) Addresses Data & Instructions The History of Computing © London Grid for Learning www. HOC. lgfl. net Main Memory (RAM)

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic Unit ALU Memory Address Register MAR Addresses Accumulator ACC Status Register SR Memory Data Register MDR The Memory Address Register MAR holds the memory location currently being accessed Data & Instructions

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic Unit ALU Memory Address Register MAR Addresses Accumulator ACC Status Register SR Memory Data Register MDR The Memory Data Register MDR holds the data from memory (or ready to be copied into memory) Instructions & data

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic Unit ALU Memory Address Register MAR Addresses Accumulator ACC Status Register SR Memory Data Register MDR The Current Instruction Register CIR holds the current instruction being processed Data & Instructions

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic Unit ALU Memory Address Register MAR Addresses Accumulator ACC Status Register SR Memory Data Register MDR The Arithmetic & Logic Unit ALU does the actual calculations and maths on the data being processed Data & Instructions

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic

Central Processing Unit (CPU) Program Counter PC Current Instruction Register CIR Arithmetic & Logic Unit ALU Memory Address Register MAR Addresses Accumulator ACC Status Register SR Memory Data Register MDR The Accumulator ACC holds the results of any calculations made by the ALU Data & Instructions

Fetch Decode Execute Cycle Summary Fetch Phase 1. The address of the next instruction

Fetch Decode Execute Cycle Summary Fetch Phase 1. The address of the next instruction is copied from the PC to the MAR. 2. The instruction held at that address is copied to the MDR. Simultaneously the PC is incremented (so it holds the address of the next instruction). 3. The contents of the MDR are copied to the CIR. Decode Phase The instruction in the CIR is decoded Execute Phase The instruction is executed The History of Computing © London Grid for Learning www. HOC. lgfl. net

Identifying Components CPUs Central Processors The History of Computing © London Grid for Learning

Identifying Components CPUs Central Processors The History of Computing © London Grid for Learning www. HOC. lgfl. net

Identifying Components Heat sinks and fans

Identifying Components Heat sinks and fans

Identifying Components Motherboards

Identifying Components Motherboards

Identifying Components Motherboard buses

Identifying Components Motherboard buses

Identifying Components RAM – Random Access Memory

Identifying Components RAM – Random Access Memory

Identifying Components Hard Drives The History of Computing © London Grid for Learning www.

Identifying Components Hard Drives The History of Computing © London Grid for Learning www. HOC. lgfl. net

Identifying Components Power Supply Units - PSU

Identifying Components Power Supply Units - PSU

Introduction aux microprocesseurs Fetch decode execute fetch decodeIntroduction aux microprocesseurs Fetch decode execute fetch decode
Introduction aux microprocesseurs Fetch decode execute fetch decodeIntroduction aux microprocesseurs Fetch decode execute fetch decode
Instruction Cycle Two steps Fetch Execute Fetch CycleInstruction Cycle Two steps Fetch Execute Fetch Cycle
Instruction Execution fetch cycle hmtfas fetch execute cycleInstruction Execution fetch cycle hmtfas fetch execute cycle
DLX Instruction Fetch Execute Addr Calc Instr DecodeDLX Instruction Fetch Execute Addr Calc Instr Decode
DLX Instruction Fetch Execute Addr Calc Instr DecodeDLX Instruction Fetch Execute Addr Calc Instr Decode
Central Processing Unit Fetch Cycle FETCH Programming CounterCentral Processing Unit Fetch Cycle FETCH Programming Counter
DATA PATH fetch and execute cycle Organisasi ProsesorDATA PATH fetch and execute cycle Organisasi Prosesor
Previously l l Fetch execute cycle Pipelining andPreviously l l Fetch execute cycle Pipelining and
Instruction Cycle Main Topics Instruction fetch Instruction executeInstruction Cycle Main Topics Instruction fetch Instruction execute
Fetch Execute Cycle In Detail Simple Layout ofFetch Execute Cycle In Detail Simple Layout of
Advanced Topics 1 Processor Instruction fetch n DecodeAdvanced Topics 1 Processor Instruction fetch n Decode
Processor Microarchitecture Fetch Decode ExecuteWriteback Register Files ALUProcessor Microarchitecture Fetch Decode ExecuteWriteback Register Files ALU
Chapter 3 e Fetch and Decode Stages McChapter 3 e Fetch and Decode Stages Mc
Slicer 3 Webservices Infrastructure Fetch Medical Informatics FetchSlicer 3 Webservices Infrastructure Fetch Medical Informatics Fetch
RISC 5 Decode EXecute Writeback Store Memory ALURISC 5 Decode EXecute Writeback Store Memory ALU
Database Background Process Instance Parse Execute Fetch ServerDatabase Background Process Instance Parse Execute Fetch Server
SQLTRACE SQL n n l PARSING EXECUTE FETCHSQLTRACE SQL n n l PARSING EXECUTE FETCH
Water Cycle Carbon Cycle Phosphorous Cycle Nitrogen CycleWater Cycle Carbon Cycle Phosphorous Cycle Nitrogen Cycle
Water Cycle Carbon Cycle Phosphorous Cycle Nitrogen CycleWater Cycle Carbon Cycle Phosphorous Cycle Nitrogen Cycle
PIPELINING 7122013 FETCHEXECUTE CYCLE 1 Fetch next instructionPIPELINING 7122013 FETCHEXECUTE CYCLE 1 Fetch next instruction
THE FETCHEXECUTE CYCLE REGISTERS Check for interrupts FetchTHE FETCHEXECUTE CYCLE REGISTERS Check for interrupts Fetch
Technology Technology Overview Video Quality Improvements Post DecodeTechnology Technology Overview Video Quality Improvements Post Decode
Digital Decode Correction Logic Preliminary design review PAYALDigital Decode Correction Logic Preliminary design review PAYAL