CGS 3269 Pipelining Pipelining Load Store Instruction Fetch

CGS 3269 Pipelining

Pipelining – Load Store Instruction Fetch T 0 T 1 T 2 T 3 Fetch I 1 I 2 I 3 Execute

2 Stages Fetch Mar PC MDR IM[MAR] IR MDR PC + 1 Decoder IR. OP Exec A R 1 B R 2 ALU A (op) B C ALU (results) R 3 C Fetch Unit MAR IM MDR IR

Further Pipelining Instruction Fetch ID / OF: Instruction decode operand fetch T 0 T 1 T 2 T 3 T 4 T 5 T 6 Fetch I 0 I 1 I 2 I 3 I 4 ID/OF Exec I 0 I 1 I 2 I 3 I 4 Execute

3 Stages Fetch Mar PC MDR IM[MAR] IR MDR PC + 1 ID / OF Decoder IR. OP A R 1 B R 2 Exec ALUop A (op) B C ALUop R 3 C

4 Stages Instruction Fetch ID / OF Exec. T 0 T 1 T 2 T 3 T 4 IF OF Exec WB I 0 T 5 Write Back T 6 I 1 I 2 I 3 I 4 I 0 I 1 I 2 I 3 I 4 I 1 I 2 I 3 T 7 I 4

4 Stages Fetch Mar PC MDR IM[MAR] IR MDR PC + 1 ID / OF Decoder IR. OP A R 1 B R 2 Exec ALUop A (op) B C ALUop WB R 3 C *could have conflict with OF and WB

4 Stages Example Register Files R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 V 3 = V 1 + V 2 I. M. IF MAR PC M MDR V 1 V 2 There is a conflict in OF and WB because both are trying to access the register file R 1 V 2 R 3 V 1 OF + R 3 R 2 R 1 EXEC. R 3 V 3 WB + OF R 3 V 2 V 1 A V 2 C V 3 V 1 B R 3 V 3 WB

5 Stages Inst. Fetch ID / OF Inst. Memory Exec. Mem Data Memory Register File WB

Load (5 stages) Load Reg, Adrr IF Inst. Fetch ID / OF Exec Mem WB Might Need To Offset Gets Value From Data Mem. Write Value back To Reg.

Add (5 stages) ADD R 3, R 1, R 2 IF Inst. Fetch ID / OF Exec V 1 = R 1 V 2 = R 2 V 3 gets V 1 + V 2 Mem WB R 3 Gets V 3

Store (5 stages) STORE Adrr, Reg Inst. IF ID / OF Exec Mem Fetch V 1 Gets Reg Calculate Effective Address Adrr Gets V 1 WB

CGS 3269 Pipelining