Lecture 3 Combinational Automatic TestPattern Generation ATPG n
Lecture 3 Combinational Automatic Test-Pattern Generation (ATPG) n n n ATPG System Representations Completeness Algebras Types of Algorithms Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 1
ATPG Problem n ATPG: Automatic test pattern generation Given n n A circuit (usually at gate-level) A fault model (usually stuck-at type) Find n n n A set of input vectors to detect all modeled faults. Core problem: Find a test vector for a given fault. Combine the “core solution” with a fault simulator into an ATPG system. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 2
What is Test? Fault activation Fault effect Primary inputs (PI) X 1 0 0 1 X X Combinational circuit 1/0 Stuck-at-0 fault Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 1/0 Primary outputs (PO) Path sensitization 3
ATPG is a Search Problem n Search the input vector space for a test: n n Vector Space Initialize all signals to unknown (X) state – complete vector space is the playing field Activate the given fault and sensitize a path to a PO – narrow down to one or more tests Vector Space Circuit X X X Circuit X 0 sa 1 1 001 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 sa 1 0/1 101 4
Need to Deal With Two Copies of the Circuit Good circuit Same input 0 1 Faulty circuit X X 0 1 sa 1 Copyright 2001, Agrawal & Bushnell Different outputs X X 0 Alternatively, use a multi-valued algebra of signal values for both good and faulty circuits. 1 Circuit 1 VLSI Test: Lecture 3 X X 0 sa 1 0/1 5
Circuit and Binary Decision Tree Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 6
Binary Decision Diagram n n n BDD – Follow path from source to sink node – product of literals along path gives Boolean value at sink Rightmost path: A B C = 1 Problem: Size varies greatly with variable order Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 7
Algorithm Completeness n n n Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test Untestable fault – no test for it even after entire tree searched Combinational circuits only – untestable faults are redundant, showing the presence of unnecessary hardware Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 8
Algebras: Roth’s 5 -Valued and Muth’s 9 -Valued Symbol D D 0 1 X G 0 G 1 F 0 F 1 Fault-free Faulty Alternative Representation circuit Circuit 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Copyright 2001, Agrawal & Bushnell 1 0 0 1 X X VLSI Test: Lecture 3 0 1 X X X 0 1 Roth’s Algebra Muth’s Additions 9
Roth’s and Muth’s Higher-Order Algebras n n n Represent two machines, which are simulated simultaneously by a computer program: § Good circuit machine (1 st value) § Bad circuit machine (2 nd value) Better to represent both in the algebra: § Need only 1 pass of ATPG to solve both § Good machine values that preclude bad machine values become obvious sooner & vice versa Needed for complete ATPG: § Combinational: Multi-path sensitization, Roth Algebra § Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 10
Function of NAND Gate Input a c b 1 0/1 1 X D D 0 1 1 1 1 0 X D D X 1 X X D 1 D X 1 D c D Copyright 2001, Agrawal & Bushnell Input b a D 1/0 0 VLSI Test: Lecture 3 11
Exhaustive Algorithm n n For n-input circuit, generate all 2 n input patterns Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs £ § Perform exhaustive ATPG for each cone § Misses faults that require specific activation patterns for multiple cones to be tested Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 12
Random-Pattern Generation n n Flow chart for method Use to get tests for 6080% of faults, then switch to D-algorithm or other ATPG for rest Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 13
Boolean Difference Symbolic Method (Sellers et al. ) g = G (X 1, X 2, …, Xn) for the fault site fj = Fj (g, X 1, X 2, …, Xn) 1 £ j £ m Xi = 0 or 1 for 1 £ i £ n Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 14
Boolean Difference (Sellers, Hsiao, Bearnson) n Shannon’s Expansion Theorem: F (X 1, X 2, …, Xn) = X 2 · F (X 1, 1, …, Xn) + X 2 F (X 1, 0, …, Xn) · n Boolean Difference (partial derivative): Fj ¶ = Fj (1, X 2, …, Xn) Fj (0, X 1, …, Xn) Å g n ¶ Fault Detection Requirements: G (X 1, X 2, …, Xn) = 1 F ¶ j = F (1, X , …, X ) Fj (0, X 1, …, Xn) = 1 j 1 2 n Å g ¶ Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 15
Path Sensitization Method Circuit Example 1 Fault Sensitization 2 Fault Propagation 3 Line Justification Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 16
Path Sensitization Method Circuit Example § Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 1 D D 1 0 D 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 17
Path Sensitization Method Circuit Example § Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because -frontier (chain of D or D) disappears 1 1 D D D 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 18
Path Sensitization Method Circuit Example § Final try: path g – i – j – k – L – test found! 0 1 0 D D D 1 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 19
Forward Implication n n Copyright 2001, Agrawal & Bushnell Results in logic gate inputs that are significantly labeled so that output is uniquely determined AND gate forward implication table: VLSI Test: Lecture 3 20
Backward Implication n Unique determination of all gate inputs when the gate output and some of the inputs are given Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 21
Implication Stack n Push-down stack. Records: § Each signal set in circuit by ATPG § Whether alternate signal value already tried § Portion of binary search tree already searched Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 22
Implication Stack after Backtrack Unexplored Present Assignment Searched and Infeasible 0 0 Copyright 2001, Agrawal & Bushnell F 1 E 0 B VLSI Test: Lecture 3 B 0 1 F 1 1 0 F 1 23
Objectives and Backtracing of ATPG Algorithm n Objective – desired signal value goal for ATPG § Guides it away from infeasible/hard solutions n Backtrace – Determines which primary input and value to set to achieve objective § Use testability measures Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 24
Branch-and-Bound Search n n n Efficiently searches binary search tree Branching – At each tree level, selects which input variable to set to what value Bounding – Avoids exploring large tree portions by artificially restricting search decision choices § Complete exploration is impractical § Uses heuristics Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 25
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