How does CLA carry lookahead adder work Weijen

How does CLA (carry lookahead adder) work? Wei-jen Hsu TA for EE 457 at USC, fall 2004 Modified fall 2005

A simple one-bit full adder A B Cout (+) Cin S It takes A, B, and Cin as input and generates S and Cout in 2 gate delays (SOP)

4 -bit RCA A 3 B 3 C 4 (+) Carry propagation forms a long sequential wait chain, hence RCA S 3 Is slow!! A 2 B 2 C 3 (+) S 2 A 1 B 1 C 2 (+) S 1 A 0 B 0 C 1 (+) C 0 S 0 • Work from lowest bit to highest bit sequentially. • With A 0, B 0, and C 0, the lowest bit adder generates S 0 and C 1 in 2 gate delay. • With A 1, B 1, and C 1 ready, the second bit adder generates S 1 and C 2 in 2 gate delay. • Each bit adder has to wait for the lower bit adder to propagate the carry.

Observations • The critical component each bit adder waits for is the carry input. • Instead of generating and propagating carry bit-by-bit, can we generate all of them in parallel and break the sequential chain? • This is exactly the idea of CLA (carry lookahead adder).

Carry Look Ahead Logic • Now even before the carry in (Cin) is available, based on the inputs (A, B) only, can we say anything about the carry out? • Under what condition will the bit propagate an outgoing carry (Cout), if there is an incoming carry (Cin)? • Under what condition will the bit generate an outgoing carry (Cout), regardless of whethere is an incoming carry (Cin)?

1 -bit CLA adder A B S (+) p Cin g • Instead of Cout, an 1 -bit CLA adder block takes A, B inputs and generates p, g • p=propagator =>I will propagate the Cin to the next bit. p = A+B (If either A or B is 1, Cin=1 causes Cout=1) • g=generator =>I will generate a Cout independent of what Cin is. g = AB (If both A and B are 1, Cout=1 for sure) • p, g are generated in 1 gate delay after we have A, B. Note that Cin is not needed to generate p, g. • S is generated in 2 gate delay after we get Cin (SOP).

4 -bit CLA A B (+) p C 4 g A B C 3 (+) p g A B C 2 (+) p g A B C 1 (+) p C 0 g CLL (carry look-ahead logic) • The CLL takes p, g from all 4 bits and C 0 as input to generate all Cs in 2 gate delay. • C 1=g 0+p 0 C 0, • C 2=g 1+p 1 g 0+p 1 p 0 C 0, • C 3=g 2+p 2 g 1+p 2 p 1 g 0+p 2 p 1 p 0 c 0, • C 4=g 3+p 3 g 2+p 3 p 2 g 1+p 3 p 2 p 1 g 0+p 3 p 2 p 1 p 0 c 0 (Note: this C 4 is too complicated to generate in 2 -level SOP representation)

4 -bit CLA A 3 B 3 S 3 (+) p 3 g 3 A 2 B 2 C 3 S 2 (+) p 2 g 2 A 1 B 1 C 2 S 1 (+) p 1 g 1 A 0 B 0 (+) C 1 S 0 p 0 C 0 g 0 CLL (carry look-ahead logic) • Given A, B’s, all p, g’s are generated in 1 gate delay in parallel. • Given all p, g’s, all C’s are generated in 2 gate delay in parallel. • Given all C’s, all S’s are generated in 2 gate delay in parallel. • Key virtue of CLA: sequential operation in RCA is broken into parallel operation!!

Observation • The CLL block cannot be made too big (at most 4 bits) because if the equations for C’s are too long it cannot be evaluated in 2 gate delay. • So how about long operands, say 16 bits? • We add another layer of CLL and make a multi-level CLA.

16 -bit CLA • Same as before, p, g’s are generated in parallel in 1 gate delay • Now, without input carry, the first-tier CLL cannot generate C’s…… Instead they generate P, G’s (group propagator and group generator) in 2 gate delay P => This group will propagate the input carry to the group P=p 0 p 1 p 2 p 3 G => This group will generate a output carry G=g 3+p 3 g 2+p 3 p 2 g 1+p 3 p 2 p 1 g 0 • The second-tier CLL takes the P, G’s from first-tier CLLs and C 0 to generate “seed C’s” for first-tier CLLs in 2 gate delay. (note that the logic for generating “seed C’s” from P, G’s is exactly the same to generating C’s from p, g’s!) • With the seed C’s as input, the first-tier CLLs use Cin and p, g’s to generate C’s in 2 gate delay Therefore, totally • With all C’s in place, S’s are calculated in 2 gate delay 1+2+2=9 gate delay to finish the whole thing!!

Now, how about 64 -bit CLA? • You can visualize that in mind by yourself now, I guess.

A bit more details A 3 B 3 S 3 (+) p 3 C 4 g 3 A 2 B 2 C 3 S 2 (+) p 2 g 2 A 1 B 1 C 2 S 1 (+) p 1 g 1 A 0 B 0 C 1 S 0 (+) p 0 C 0 g 0 CLL (carry look-ahead logic) • Do all these 4 S’s (S 3, S 2, S 1, S 0) come together? Actually no! Since C 0 is available from the beginning, S 0 can be calculated in 2 gate delays (using original SOP expression for S bit in a single bit adder) (before S 3, S 2, S 1)

A bit more details (Cont’d) C 0 • Again, actually not all the S’s come together! • C 0 is readily available, so S 0 can be calculated in 2 gate delays. • Since C 0 is readily available, the lowest first-tier CLL can generate C 1, C 2, C 3 independent of the second-tier CLL. Since C 1, C 2, C 3 are done earlier, so is S 1, S 2, S 3. (in 5 gate delays. 1 for (p, g), 2 for (C 1, C 2, C 3), 2 for S) • When we get C 4, C 8, C 12, we can start to calculate S 4, S 8, S 12 and get them in 2 more gate delays. That is the same time when we get the other C’s (purple guys) at 7 gate delays. • Timing for items generated (in terms of gate delay): black=already available (and special case for S 0=4), orange=1, green=3, blue=5, purple=7, brown=9

Thanks!! (You can distribute these slides as one whole file to anywhere you feel it may be useful. )