HiPBD Hierarchical PlatformBased Design Method research implementation Speaker
Hi-PBD: Hierarchical Platform-Based Design Method ----research & implementation Speaker: Zhihui Xiong VLSI Lab. National University of Defense Technology Changsha, China Jihua Chen , Zhihui Xiong, Sikun Li 1
Outline v Related Work Ø mainstream VLSI design methodologies Ø existing co-design environments Ø drawbacks v Research on Hi-PBD v YH-PBDE: Implementation of Hi-PBD method v Conclusions & Future Work 2
v Related Work Ø mainstream VLSI design methodologies ü Timing-Driven Design: TDD, deep sub-micro ASIC design ü Block-Based Design: BBD, supports IP reuse ü Platform-Based Design: PBD, supports system reuse, including reuse of IPs, models, tools, libraries and design flows 3
v Related Work (cont. ) Ø existing co-design environments ü VULCAN: by R. K. Gupta, 1993, Stanford University. ü COSYMA : by R. Ernst, 1996, Tech. Univ. of Braunschweig ü since then, others including: Ptolemy, Polis, Pea. CE, … ü SCE: by D. D. Gajski, 2003, TIMA Lab. France ü some commercial tools • Cadence VCC • Co. Ware N 2 C • Synopsys Co. Centric Studio 4
v Related Work (cont. ) Ø drawbacks ü no real separation of design concerns • no separation of function from structure • no separation of computation from communication ü little support for Platform-Based Design methodology ü mainly support IP level reuse, not system level reuse ü only support some phases of So. C design, and little support for the overall phases 5
Outline v Related Work v Research on Hi-PBD Ø ideas Ø overall structure Ø more words on Virtual Components Level Ø features v YH-PBDE: Implementation of Hi-PBD method v Conclusions & Future Work 6
v Research on Hi-PBD Ø ideas first of all, let’s see a “true” story…… One day, Bill Gates discovered a big bag of dollars. However, it is too high to get it directly. 7
v Research on Hi-PBD Ø ideas first of all, let see a “true” story…… (cont. ) After some consideration, he decided to use a ladder. 8
v Research on Hi-PBD Ø ideas first of all, let see a “true” story…… (cont. ) Then, he climbed towards the dollars. 9
v Research on Hi-PBD Ø ideas first of all, let see a “true” story…… (cont. ) Finally, he got the bag of dollars, and became the richest man in the world. 10
v Research on Hi-PBD Ø ideas now, a similar thing happens with So. C design …… since too many things to be done: • Hw/Sw partitioning • co-simulation • performance evaluation • hardware & interface synthesis • embedded software generation • …… 11
v Research on Hi-PBD Ø ideas now, a similar thing happens with So. C design …… • hardware & interface synthesis • embedded software generation • Hw/Sw partitioning 12
v Research on Hi-PBD Ø overall structure ü 3 design levels ü 2 design mappings • system modeling level • design planning • virtual components level • virtual-real synthesis ü 1 platform library • to achieve system level reusability • real components level 13
v Research on Hi-PBD Ø overall structure (cont. ) system modeling level (SML) ü describes function and performance of So. C at algorithm level ü system modeling based on CTG model • CTG: Constrained Taskflow Graph • Hierarchical FSM + coarse grained CDFG + performance constraint 14
v Research on Hi-PBD Ø overall structure (cont. ) Virtual Components Level (VCL) ü abstracts the RTL So. C system architecture ü serves as a connecting link between the system modeling level and real components level ü avoids direct synthesis from system model to the final So. C target • virtual hardware components (VHw. IPs) • virtual software components (VSw. IPs) • virtual communicator components (VCommu. IPs) 15
v Research on Hi-PBD Ø overall structure (cont. ) Real Components Level (RCL) ü RTL Hw/Sw So. C system ü HW part: hardware accelerator modules (such as co-processor, DSP, ASIC), Input/Output controller devices ü SW part: RTOS, device driver, application processes ü fast prototyping based on FPGA board, for RTL simulation and performance analysis 16
v Research on Hi-PBD Ø overall structure (cont. ) 2 design mappings ---- mapping L 0 -L 1 ü the mapping from System Modeling Level to Virtual Components Level, we call it Design Planning ü some tasks are partitioned to hardware ü other tasks are partitioned to software 17
v Research on Hi-PBD Ø overall structure (cont. ) 2 design mappings ---- mapping L 1 -L 2 ü mapping from Virtual Components Level to Real Components Level, we call it Virtual-Real Synthesis ü virtual hardware is synthesized to real (RTL) hardware ü virtual software is synthesized to embedded process ü virtual communicator is synthesized to On-Chip Bus 18
v Research on Hi-PBD Ø more words on Virtual Components Level virtual component model ü structure part • construct “virtual design” • for partitioning • for synthesis ü behavior part • for software generation • for co-simulation • for verification & evaluation 19
v Research on Hi-PBD Ø more words on Virtual Components Level (cont. ) modeling hardware at VCL ü a simple module (adder) ü a more complex module ü modeling of these two modules 20
v Research on Hi-PBD Ø more words on Virtual Components Level (cont. ) modeling software at VCL ü wrap software process using System. C module • process (task) template in u. C/OS II • adder example process • wrapped adder • variables and external APIs are mapped to ports • normal statements are mapped to behaviors • RTOS services are mapped to System. C core 21
v Research on Hi-PBD Ø more words on Virtual Components Level (cont. ) modeling communication at VCL ü connects multiple V. C. s ü message transmitting flow step 1: consumer 2 requires data from producer 0 step 2: communicator transmits the message to producer 0 step 3: producer 0 receives data requirement step 4: producer 0 sends data to consumer 2 step 5: communicator transmits the message to consumer 2 step 6: consumer 2 receives the data 22
v Research on Hi-PBD Ø features ü hierarchical design flow • 3 design levels • 2 mappings ü supports system level reuse well • enables reuse of design templates on each design level • enable reuse of mapping process & mapping results ü achieves separation of design concerns • separation of function from structure • separation of computation from communication 23
Outline v Related Work v Research on Hi-PBD v YH-PBDE: Implementation of Hi-PBD method Ø architecture Ø performance & power estimation Ø snapshots v Conclusions & Future Work 24
v YH-PBDE: Implementation of Hi-PBD method Ø architecture ü modeling/simulation & mapping tools • do modeling and simulation at the three design levels • do mapping between design levels ü helper tools ü platform manager • for system level reuse 25
v YH-PBDE: Implementation of Hi-PBD method Ø performance & power estimation ü apply different estimation methods for different levels ü estimation at System Modeling Level • based on combination of Simple. Scalar and Sim-Wattch • and made some improvements ü estimation at Virtual Components Level • establish performance character for each virtual component • establish power character for each virtual component • while simulating on System. C core, calculate performance and power ü estimation at Real Components Level • performance are estimated via FPGA development suites • Power(system) = Power(Sw) + Power(Hw) 26
v YH-PBDE: Implementation of Hi-PBD method Ø snapshots system modeling, task attribute editor 27
v YH-PBDE: Implementation of Hi-PBD method Ø snapshots (cont. ) system modeling, task. FSM editor 28
v YH-PBDE: Implementation of Hi-PBD method Ø snapshots (cont. ) virtual components editor 29
v YH-PBDE: Implementation of Hi-PBD method Ø snapshots (cont. ) real components editor 30
v YH-PBDE: Implementation of Hi-PBD method Ø snapshots (cont. ) partitioning interface 31
Outline v Related Work v Research on Hi-PBD v YH-PBDE: Implementation of Hi-PBD method v Conclusions & Future Work 32
v Conclusions & Future Work Ø Conclusions ü Hi-PBD method improves high level design efficiency ü Introduction of Virtual Components Level makes it more easy to do So. C high level design ü The implemented environment supports Hi-PBD well Ø Future Work ü to do more research on Virtual-Real Synthesis ü to do more work on embedded software generation ü to do more work on power-aware Hi-PBD method 33
Thank you 34
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