Computer Architecture A Quantitative Approach Fifth Edition Chapter

n Thread-Level parallelism n n n Introduction Have multiple program counters Uses MIMD model

n Symmetric multiprocessors (SMP) n n n Introduction Types Small number of cores Share

Centralized Memory Multiprocessor • • Also called symmetric multiprocessors (SMPs) because single main memory

Distributed Memory Multiprocessor • Pro: Cost-effective way to scale memory bandwidth • • If

Communication and Memory Architecture 1. 2. Communication occurs by explicitly passing messages among the

Challenges of Parallel Processing 1. 2. n Application parallelism primarily via new algorithms that

Processors may see different values through their caches: Copyright © 2012, Elsevier Inc. All

Example Cache Coherence Problem P 1 $ P 2 u= ? P 3 4

n Coherence n n n Consistency n n n All reads by any processor

A memory system is coherent if n n n A read by P of

Try it Come up with examples: a. coherent, but not consistent b. consistent, but

Rules n n A write does not complete (and allow the next write to

n Coherent caches provide: n n n Migration: movement of data Replication: multiple copies

Basic Schemes for Enforcing Coherence n Program on multiple processors will normally have copies

n Write invalidate n n On write, invalidate all other copies Use bus to

n Locating an item when a read miss occurs n n In write-back cache,

Copyright © 2012, Elsevier Inc. All rights reserved. Centralized Shared-Memory Architectures Snoopy Coherence Protocols

Two Classes of Cache Coherence Protocols 1. 2. Directory based — Sharing status of

Snoopy Cache-Coherence Protocols State Address Data n Cache Controller “snoops” all transactions on the

Example: Write-thru Invalidate P 1 $ P 2 u= ? P 3 4 $

Architectural Building Blocks n Cache block state transition diagram n n Broadcast Medium Transactions

Locate up-to-date copy of data n Write-through: get up-to-date copy from memory n n

Cache Resources for WB Snooping n n Normal cache tags can be used for

Cache Resources for WB Snooping n To track whether a cache block is shared,

Cache behavior in response to bus n Every bus transaction must check the cache-address

Key concept Invalidate all other processors’ copies before writing. Stated another way: gain exclusive

Example Protocol n n Snooping coherence protocol is usually implemented by incorporating a finite-state

Write-through Invalidate Protocol n 2 states per block in each cache n n n

Is 2 -state Protocol Coherent? n n Processor only observes state of memory system

Ordering Writes establish a partial order n Doesn’t constrain ordering of reads, though shared-medium

Example Write Back Snoopy Protocol n Invalidation protocol, write-back cache n n n Each

Write-Back State Machine CPU Read hit n n State machine for CPU requests for

Write-Back State Machine- Bus request n State machine for bus requests for each cache

Block-replacement n State machine for CPU requests for each cache block Invalid Italics indicate

Write-back State Machine: showing all transitions n CPU Read hit State machine for CPU

Example Assumes A 1 and A 2 map to same cache block, initial cache

Example Assumes A 1 and A 2 map to same cache block CSE 820

Example Assumes A 1 and A 2 map to same cache block, but A

n Complications for the basic MSI protocol: n Operations are not atomic n n

n Shared memory bus and snooping bandwidth is bottleneck for scaling symmetric multiprocessors n

n AMD Opteron: n n n Memory directly connected to each multicore chip in

n Coherence influences cache miss rate n Coherence misses n True sharing misses n

Copyright © 2012, Elsevier Inc. All rights reserved. Performance of Symmetric Shared-Memory Multiprocessors Performance

n Directory keeps track of every block n n n Implement in shared L

n For each block, maintain state: n Shared n n Uncached Modified n n

Copyright © 2012, Elsevier Inc. All rights reserved. Distributed Shared Memory and Directory-Based Coherence

n For uncached block: n Read miss n n Write miss n n Requesting

n For exclusive block: n Read miss n n Data write back n n

n Basic building blocks: n Atomic exchange n n Swaps register with memory location

Synchronization Implementing Locks n Spin lockit: If no coherence: DADDUI EXCH BNEZ R 2,

n Advantage of this scheme: reduces memory traffic Copyright © 2012, Elsevier Inc. All

Processor 1: A=0 … A=1 if (B==0) … n Should be impossible for both

n To implement, delay completion of all memory accesses until all invalidations caused by

n Rules: n X→Y n n Operation X must complete before operation Y is

n n n Consistency model is multiprocessor specific Programmers will often implement explicit synchronization

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n Thread-Level parallelism n n n Introduction Have multiple program counters Uses MIMD model Targeted for tightly-coupled, shared-memory multiprocessors For n processors, need n threads Amount of computation assigned to each thread = grain size n Threads can be used for data-level parallelism, but the overhead may outweigh the benefit. Copyright © 2012, Elsevier Inc. All rights reserved. 2

n Symmetric multiprocessors (SMP) n n n Introduction Types Small number of cores Share single memory with uniform memory latency Distributed shared memory (DSM) n n n Memory distributed among processors Non-uniform memory access/latency (NUMA) Processors connected via direct (switched) and nondirect (multi-hop) interconnection networks Copyright © 2012, Elsevier Inc. All rights reserved. 3

Centralized Memory Multiprocessor • • Also called symmetric multiprocessors (SMPs) because single main memory has a symmetric relationship to all processors Large caches single memory can satisfy memory demands of small number of processors Can scale to a few dozen processors by using a switch and by using many memory banks Although scaling beyond that is technically conceivable, it becomes less attractive as the number of processors sharing centralized memory increases CSE 820 4 4

Distributed Memory Multiprocessor • Pro: Cost-effective way to scale memory bandwidth • • If most accesses are to local memory Pro: Reduces latency of local memory accesses Con: Communicating data between processors more complex Con: Must change software to take advantage of increased memory BW CSE 820 5 5

Communication and Memory Architecture 1. 2. Communication occurs by explicitly passing messages among the processors: message-passing multiprocessors Communication occurs through a shared address space (via loads and stores): shared memory multiprocessors either • • n UMA (Uniform Memory Access time) for shared address, centralized memory MP NUMA (Non Uniform Memory Access time multiprocessor) for shared address, distributed memory MP In past, confusion whether “sharing” means CSE 820 6 MP) or sharing physical memory (Symmetric 6

Challenges of Parallel Processing 1. 2. n Application parallelism primarily via new algorithms that have better parallel performance Long remote latency impact both by architect and by the programmer For example, reduce frequency of remote accesses either by n n n Caching shared data (HW) Restructuring the data layout to make more accesses local (SW) Today’s lecture on HW to help latency via caches CSE 820 7 7

Example Cache Coherence Problem P 1 $ P 2 u= ? P 3 4 $ 5 $ u : 5 u= 7 u : 5 1 3 u= ? 2 u : 5 I/O devices Memory n n n Processors see different values for u after event 3 With write-back caches, value written back to memory depends on happenstance of which cache flushes or writes back value n Processes accessing main memory may see very stale value Unacceptable for programming, and its frequent! CSE 820 9 9

n Coherence n n n Consistency n n n All reads by any processor must return the most recently written value. Writes to the same location by any two processors are seen in the same order by all processors. When a written value will be returned by a read If a processor writes location A followed by location B, any processor that sees the new value of B must also see the new value of A. Centralized Shared-Memory Architectures Cache Coherence: same memory location Consistency: different memory locations Copyright © 2012, Elsevier Inc. All rights reserved. 10

A memory system is coherent if n n n A read by P of X that follows a write by P of X, with no other write of X by another processor occurring between the write and the read by P, always returns the value written by P. A read by P of X that follows a write to X by another processor returns the written value, if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses. Writes to the same location are serialized; i. e. two writes to the same location by any two processors are seen in the same order by all processors. Copyright © 2012, Elsevier Inc. All rights reserved. 11

Rules n n A write does not complete (and allow the next write to occur) until all processors have seen the effect of that write. The processor does not change the order of any write with respect to any other memory access. Effectively: a processor is allowed to reorder reads, but is forced to finish writes in program order. Copyright © 2012, Elsevier Inc. All rights reserved. 13

n Coherent caches provide: n n n Migration: movement of data Replication: multiple copies of data Cache coherence protocols n Directory based n n Sharing status of each block kept in one location Snooping n Centralized Shared-Memory Architectures Enforcing Coherence Each core tracks sharing status of each block Copyright © 2012, Elsevier Inc. All rights reserved. 14

Basic Schemes for Enforcing Coherence n Program on multiple processors will normally have copies of the same data in several caches n n Rather than trying to avoid sharing in SW, SMPs use a HW protocol to maintain coherent caches n n Migration and Replication key to performance of shared data Migration - data can be moved to a local cache and used there in a transparent fashion n n Unlike I/O, where its rare Reduces both latency to access shared data that is allocated remotely and bandwidth demand on the shared memory Replication – for shared data being 820 15 a copy simultaneously read, CSE since caches make 15

n Write invalidate n n On write, invalidate all other copies Use bus to serialize n n Write cannot complete until bus access is obtained Centralized Shared-Memory Architectures Snoopy Coherence Protocols Write update n On write, update all copies Copyright © 2012, Elsevier Inc. All rights reserved. 16

n Locating an item when a read miss occurs n n In write-back cache, the updated value must be sent to the requesting processor Cache lines marked as shared or exclusive/modified n Only writes to shared lines need an invalidate broadcast n Centralized Shared-Memory Architectures Snoopy Coherence Protocols After this, the line is marked as exclusive Copyright © 2012, Elsevier Inc. All rights reserved. 17

Two Classes of Cache Coherence Protocols 1. 2. Directory based — Sharing status of a block of physical memory is kept in just one location, the directory Snooping — Every cache with a copy of data also has a copy of sharing status of block, but no centralized state is kept • • All caches are accessible via some broadcast medium (a bus or switch) All cache controllers monitor or snoop on the medium to determine whether or not they have a copy of a block that is requested on a bus or switch access CSE 820 20 20

Snoopy Cache-Coherence Protocols State Address Data n Cache Controller “snoops” all transactions on the shared medium (bus or switch) n n relevant transaction if for a block it contains take action to ensure coherence n invalidate, update, or supply value depends on state of the block and the protocol Either get exclusive access before write via write invalidate or update all copies 21 on write CSE 820 21

Example: Write-thru Invalidate P 1 $ P 2 u= ? P 3 4 $ 5 $ u : 5 u= 7 u : 5 1 3 u= ? u : 5 u=7 2 I/O devices Memory n n Must invalidate before step 3 Write update uses more broadcast medium BW 820 22 all recent MPUs. CSEuse write invalidate 22

Architectural Building Blocks n Cache block state transition diagram n n Broadcast Medium Transactions (e. g. , bus) n n n n Fundamental system design abstraction Logically single set of wires connect several devices Protocol: arbitration, command/addr, data Every device observes every transaction Broadcast medium enforces serialization of read or write accesses Write serialization n n FSM specifying how disposition of block changes n invalid, dirty 1 st processor to get medium invalidates others copies Implies cannot complete write until it obtains bus All coherence schemes require serializing accesses to same cache block Also, need to find up-to-date copy of cache block CSE 820 23 23

Locate up-to-date copy of data n Write-through: get up-to-date copy from memory n n Write-back is harder n n Most recent copy can be in a cache Can use same snooping mechanism 1. 2. n n Write through simpler if enough memory BW Snoop every address placed on the bus If a processor has dirty copy of requested cache block, it provides it in response to a read request and aborts the memory access Complexity from retrieving cache block from a processor cache, which can take longer than retrieving it from memory CSE 820 24 Write-back needs lower memory bandwidth 24

Cache Resources for WB Snooping n n Normal cache tags can be used for snooping Valid bit per block makes invalidation easy Read misses easy since rely on snooping Writes Need to know if any other copies of the block are cached n n No other copies No need to place write on bus for WB Other copies Need to place invalidate on bus CSE 820 25 25

Cache Resources for WB Snooping n To track whether a cache block is shared, add extra state bit associated with each cache block, like valid bit and dirty bit n n Write to Shared block Need to place invalidate on bus and mark cache block as private (if an option) No further invalidations will be sent for that block This processor called owner of cache block Owner then changes state from shared to unshared (a. k. a. exclusive) CSE 820 26 26

Cache behavior in response to bus n Every bus transaction must check the cache-address tags n n A way to reduce interference is to duplicate tags n n could potentially interfere with processor cache accesses One set for cache access, one set for bus accesses Another way to reduce interference is to use L 2 tags Since L 2 less heavily used than L 1 Every entry in L 1 cache must be present in the L 2 cache, called the inclusion property n If Snoop gets a hit in L 2 cache, then it must arbitrate for the L 1 cache to update the state and possibly retrieve the data, which usually requires a stall of the processor n CSE 820 27 27

Key concept Invalidate all other processors’ copies before writing. Stated another way: gain exclusive ownership before writing. CSE 820 28 28

Example Protocol n n Snooping coherence protocol is usually implemented by incorporating a finite-state controller in each node Logically, think of a separate controller associated with each cache block n n That is, snooping operations or cache requests for different blocks can proceed independently In implementations, a single controller allows multiple operations to distinct blocks to proceed in interleaved fashion n that is, one operation may be initiated before another is completed, even through only one cache access or one bus access is allowed at time CSE 820 29 29

Write-through Invalidate Protocol n 2 states per block in each cache n n n as in uniprocessor state of a block is a p-vector of states Pr. Rd / Bus. Rd Hardware state bits associated with blocks Pr. Wr / Bus. Wr I that are in the cache other blocks can be seen as being in invalid (not-present) state in that cache Writes invalidate all other cache copies n V Pr. Rd: Processor Read can have multiple simultaneous readers of Processor Write block, but write. Pr. Wr: invalidates them Bus. Rd: Bus Read Bus. Wr: Bus Write CSE 820 State Tag Data Bus. Rd / Pr. Rd/ Pr. Wr / Bus. Wr / - Bus. Wr / Bus. Rd / State Tag Data P 1 Pn $ $ Bus Mem I/O devices 30

Is 2 -state Protocol Coherent? n n Processor only observes state of memory system by issuing memory operations Assume bus transactions and memory operations are atomic and a one-level cache n n all phases of one bus transaction complete before next one starts processor waits for memory operation to complete before issuing next with one-level cache, assume invalidations applied during bus transaction All writes go to bus + atomicity Writes serialized by order in which they appear on bus (bus order) => invalidations applied to caches in bus order n n How to insert reads in this order? n n n Important since processors see writes through reads, so determines whether write serialization is satisfied But read hits may happen independently and do not appear on bus or enter directly in bus order Let’s understand other ordering issues CSE 820 31 31

Ordering Writes establish a partial order n Doesn’t constrain ordering of reads, though shared-medium (bus) will order read misses too n n any order among reads between writes is fine, as long as in program order CSE 820 32 32

Example Write Back Snoopy Protocol n Invalidation protocol, write-back cache n n n Each memory block is in one state: n n n n Clean in all caches and up-to-date in memory (Shared) OR Dirty in exactly one cache (Exclusive) OR Not in any caches Each cache block is in one state (track these): n n Snoops every address on bus If it has a dirty copy of requested block, provides that block in response to the read request and aborts the memory access Shared : block can be read Exclusive : cache has the only copy, its writeable, and dirty Invalid : block contains no data (in uniprocessor cache too) Read misses: cause all caches to snoop bus Writes to clean blocks are treated as misses CSE 820 33 33

Write-Back State Machine CPU Read hit n n State machine for CPU requests for each cache block Non-resident blocks invalid Invalid CPU Read Shared Place read miss(read/onl y) on bus CPU Write Place Write Miss on Bus Cache Block State Exclusive CPU read hit (read/writ e) CPU write hit CSE 820 CPU Write Miss (? ) Write back cache block Place write miss on bus 34 34

Write-Back State Machine- Bus request n State machine for bus requests for each cache block Invalid Write miss for this block Write Back Block; (abort memory access) Exclusive (read/writ e) CSE 820 Write miss for this block Shared (read/onl y) Read miss for this block Write Back Block; (abort memory access) 35 35

Block-replacement n State machine for CPU requests for each cache block Invalid Italics indicate new states CPU Read hit CPU Read Shared Place read miss(read/onl y) on bus CPU Write Place Write CPU read miss Miss on bus Write back block, Place read miss on bus CPU Read miss Place read miss on bus CPU Write Place Write Miss on Bus Cache Block State Exclusive CPU read hit(read/writ e) CPU write hit CSE 820 CPU Write Miss Write back cache block Place write miss on bus 36 36

Write-back State Machine: showing all transitions n CPU Read hit State machine for CPU requests for each cache block and for bus requests for each cache block Write miss for this block Shared CPU Read Invalid Place read miss (read/onl y) CPU Write on bus Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Write Back Place read miss CPU Writeon bus Block; (abort on bus Place Write Miss on Bus memory Cache Block Read miss Write Back access) for this block. Block; (abort Exclusive State memory (read/writ CPU read hit access) CPU Write Miss e) CPU write hit Write back cache block Place write miss on bus CSE 820 37 37

Example Assumes A 1 and A 2 map to same cache block, initial cache state is invalid CSE 820 38 38

Example Assumes A 1 and A 2 map to same cache block CSE 820 39 39

Example Assumes A 1 and A 2 map to same cache block CSE 820 40 40

Example Assumes A 1 and A 2 map to same cache block CSE 820 41 41

Example Assumes A 1 and A 2 map to same cache block CSE 820 42 42

Example Assumes A 1 and A 2 map to same cache block, but A 1 != A 2 CSE 820 43 43

n Complications for the basic MSI protocol: n Operations are not atomic n n E. g. detect miss, acquire bus, receive a response Creates possibility of deadlock and races One solution: processor that sends invalidate can hold bus until other processors receive the invalidate Extensions: n Add exclusive state to indicate clean block in only one cache (MESI protocol) n n Centralized Shared-Memory Architectures Snoopy Coherence Protocols Prevents needing to write invalidate on a write Owned state Copyright © 2012, Elsevier Inc. All rights reserved. 44

n Shared memory bus and snooping bandwidth is bottleneck for scaling symmetric multiprocessors n n n Duplicating tags Place directory in outermost cache Use crossbars or pointto-point networks with banked memory Copyright © 2012, Elsevier Inc. All rights reserved. Centralized Shared-Memory Architectures Coherence Protocols: Extensions 45

n AMD Opteron: n n n Memory directly connected to each multicore chip in NUMA-like organization Implement coherence protocol using point-to-point links Use explicit acknowledgements to order operations Copyright © 2012, Elsevier Inc. All rights reserved. Centralized Shared-Memory Architectures Coherence Protocols 46

n Coherence influences cache miss rate n Coherence misses n True sharing misses n n n Write to shared block (transmission of invalidation) Read an invalidated block False sharing misses n Read an unmodified word in an invalidated block Copyright © 2012, Elsevier Inc. All rights reserved. Performance of Symmetric Shared-Memory Multiprocessors Performance 47

n Directory keeps track of every block n n n Implement in shared L 3 cache n n n Which caches have each block Dirty status of each block Keep bit vector of size = # cores for each block in L 3 Not scalable beyond shared L 3 Implement in a distributed fashion: Copyright © 2012, Elsevier Inc. All rights reserved. Distributed Shared Memory and Directory-Based Coherence Directory Protocols 52

n For each block, maintain state: n Shared n n Uncached Modified n n n One or more nodes have the block cached, value in memory is up-to-date Set of node IDs Exactly one node has a copy of the cache block, value in memory is out-of-date Owner node ID Directory maintains block states and sends invalidation messages Copyright © 2012, Elsevier Inc. All rights reserved. Distributed Shared Memory and Directory-Based Coherence Directory Protocols 53

n For uncached block: n Read miss n n Write miss n n Requesting node is sent the requested data and is made the only sharing node, block is now shared The requesting node is sent the requested data and becomes the sharing node, block is now exclusive For shared block: n Read miss n n The requesting node is sent the requested data from memory, node is added to sharing set Write miss n Distributed Shared Memory and Directory-Based Coherence Directory Protocols The requesting node is sent the value, all nodes in the sharing set are sent invalidate messages, sharing set only contains requesting node, block is now exclusive Copyright © 2012, Elsevier Inc. All rights reserved. 56

n For exclusive block: n Read miss n n Data write back n n The owner is sent a data fetch message, block becomes shared, owner sends data to the directory, data written back to memory, sharers set contains old owner and requestor Block becomes uncached, sharer set is empty Write miss n Message is sent to old owner to invalidate and send the value to the directory, requestor becomes new owner, block remains exclusive Copyright © 2012, Elsevier Inc. All rights reserved. Distributed Shared Memory and Directory-Based Coherence Directory Protocols 57

n Basic building blocks: n Atomic exchange n n Swaps register with memory location Test-and-set n n Synchronization Sets under condition Fetch-and-increment n Reads original value from memory and increments it in memory n Requires memory read and write in uninterruptable instruction n load linked/store conditional n If the contents of the memory location specified by the load linked are changed before the store conditional to the same address, the store conditional fails Copyright © 2012, Elsevier Inc. All rights reserved. 58

Synchronization Implementing Locks n Spin lockit: If no coherence: DADDUI EXCH BNEZ R 2, R 0, #1 R 2, 0(R 1) R 2, lockit ; atomic exchange ; already locked? R 2, 0(R 1) R 2, lockit R 2, R 0, #1 R 2, 0(R 1) R 2, lockit ; load of lock ; not available-spin ; load locked value ; swap ; branch if lock wasn’t 0 If coherence: LD BNEZ DADDUI EXCH BNEZ Copyright © 2012, Elsevier Inc. All rights reserved. 59

Processor 1: A=0 … A=1 if (B==0) … n Should be impossible for both if-statements to be evaluated as true n n Processor 2: B=0 … B=1 if (A==0) … Delayed write invalidate? Sequential consistency: n Result of execution should be the same as long as: n n Models of Memory Consistency: An Introduction Models of Memory Consistency Accesses on each processor were kept in order Accesses on different processors were arbitrarily interleaved Copyright © 2012, Elsevier Inc. All rights reserved. 61

n To implement, delay completion of all memory accesses until all invalidations caused by the access are completed n n Reduces performance! Alternatives: n Program-enforced synchronization to force write on processor to occur before read on the other processor n Requires synchronization object for A and another for B n n “Unlock” after write “Lock” after read Copyright © 2012, Elsevier Inc. All rights reserved. Models of Memory Consistency: An Introduction Implementing Locks 62

n Rules: n X→Y n n Operation X must complete before operation Y is done Sequential consistency requires: n n Relax W → R n n “Total store ordering” Relax W → W n n R → W, R → R, W → W “Partial store order” Models of Memory Consistency: An Introduction Relaxed Consistency Models Relax R → W and R → R n “Weak ordering” and “release consistency” Copyright © 2012, Elsevier Inc. All rights reserved. 63

n n n Consistency model is multiprocessor specific Programmers will often implement explicit synchronization Speculation gives much of the performance advantage of relaxed models with sequential consistency n Basic idea: if an invalidation arrives for a result that has not been committed, use speculation recovery Copyright © 2012, Elsevier Inc. All rights reserved. Models of Memory Consistency: An Introduction Relaxed Consistency Models 64