Chapter 5 Register Transfer Languages Images courtesy of

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Chapter 5 Register Transfer Languages Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Chapter 5 Register Transfer Languages Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Chapter Outline • • • Micro-operations RTL specifications Realizing RTL specifications VHDL Images courtesy

Chapter Outline • • • Micro-operations RTL specifications Realizing RTL specifications VHDL Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Micro-operations • Specify data transfer • Do not specify conditions under which transfers occur

Micro-operations • Specify data transfer • Do not specify conditions under which transfers occur • Do not specify hardware implementation Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Example: X Y X Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Example: X Y X Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Register Transfer Language • Specify micro-operations and when they occur • Format: conditions: micro-operations

Register Transfer Language • Specify micro-operations and when they occur • Format: conditions: micro-operations Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Example: α: X Y X Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Example: α: X Y X Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Simultaneous Data Transfers α: X Y, Y Z Q D Images courtesy of Addison

Simultaneous Data Transfers α: X Y, Y Z Q D Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Invalid Simultaneous Transfers α: X Y, X Z Images courtesy of Addison Wesley Longman,

Invalid Simultaneous Transfers α: X Y, X Z Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Loading Constant Values into Registers α: X 0 β: X 1 Images courtesy of

Loading Constant Values into Registers α: X 0 β: X 1 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Making Transfers Mutually Exclusive Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Making Transfers Mutually Exclusive Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Multi-bit Data Transfers α: X Y Images courtesy of Addison Wesley Longman, Inc. Copyright

Multi-bit Data Transfers α: X Y Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Bit and Bit-range Transfers Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Bit and Bit-range Transfers Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Arithmetic and Logical Microoperations Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Arithmetic and Logical Microoperations Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Shift Micro-operations Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Shift Micro-operations Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Specifying Digital Components: D Flip-Flop Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Specifying Digital Components: D Flip-Flop Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Specifying Digital Components: JK Flip-Flop Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Specifying Digital Components: JK Flip-Flop Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Specifying Digital Components: Left Shift Register Images courtesy of Addison Wesley Longman, Inc. Copyright

Specifying Digital Components: Left Shift Register Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Specifying Simple Systems Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Specifying Simple Systems Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

System Implementation – Data Paths Images courtesy of Addison Wesley Longman, Inc. Copyright ©

System Implementation – Data Paths Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

System Implementation – Data Paths and Control Images courtesy of Addison Wesley Longman, Inc.

System Implementation – Data Paths and Control Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

System Implementation Using a Bus and 3 -State Buffers Images courtesy of Addison Wesley

System Implementation Using a Bus and 3 -State Buffers Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

System Implementation Using a Bus and a Multiplexer n o j Images courtesy of

System Implementation Using a Bus and a Multiplexer n o j Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter • Counts up when U = 1 • Count sequence: 000

Modulo 6 Counter • Counts up when U = 1 • Count sequence: 000 001 010 011 100 101 000 … • V is 3 -bit output = count value • C is 1 -bit output = 1 when V = 000 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter State Table 111 Images courtesy of Addison Wesley Longman, Inc. Copyright

Modulo 6 Counter State Table 111 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter State Diagram Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Modulo 6 Counter State Diagram Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter RTL Specification Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Modulo 6 Counter RTL Specification Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter System Implementation Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Modulo 6 Counter System Implementation Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter Another System Implementation Images courtesy of Addison Wesley Longman, Inc. Copyright

Modulo 6 Counter Another System Implementation Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller • • • C = 1 when car is at toll

Toll Booth Controller • • • C = 1 when car is at toll booth I[1. . 0] indicates coin input Outputs R, G, A: – Car in toll booth, toll not fully paid: R = 1 – Toll paid: G = 1 – Car left without paying full toll: R = 1, A = 1 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller States Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller States Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller State Table Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Toll Booth Controller State Table Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller State Diagram Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Toll Booth Controller State Diagram Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller State Assignments Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Toll Booth Controller State Assignments Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Converting State Transitions to RTL Code Images courtesy of Addison Wesley Longman, Inc. Copyright

Converting State Transitions to RTL Code Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Converting State Transitions to RTL Code Images courtesy of Addison Wesley Longman, Inc. Copyright

Converting State Transitions to RTL Code Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller RTL Specification (excluding outputs) Images courtesy of Addison Wesley Longman, Inc.

Toll Booth Controller RTL Specification (excluding outputs) Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Toll Booth Controller RTL Specification (outputs) Images courtesy of Addison Wesley Longman, Inc. Copyright

Toll Booth Controller RTL Specification (outputs) Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL – VHSIC Hardware Description Language • • • Formal syntax – portable Platform

VHDL – VHSIC Hardware Description Language • • • Formal syntax – portable Platform independent Design for PLDs, ASICs, or custom chips • Simulate designs • Different levels of abstraction Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL Design Structure • • • Library section Entity section Architecture section Images courtesy

VHDL Design Structure • • • Library section Entity section Architecture section Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL Library Section library IEEE; use IEEE. std_logic_1164. all; Images courtesy of Addison Wesley

VHDL Library Section library IEEE; use IEEE. std_logic_1164. all; Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL Entity Section Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL Entity Section Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL Architecture Section Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL Architecture Section Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL – High Level of Abstraction • Modulo 6 counter • Designed as a

VHDL – High Level of Abstraction • Modulo 6 counter • Designed as a state machine Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter – Library and Entity Sections Images courtesy of Addison Wesley Longman,

Modulo 6 Counter – Library and Entity Sections Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Modulo 6 Counter – One State Images courtesy of Addison Wesley Longman, Inc. Copyright

Modulo 6 Counter – One State Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Architecture Section – State Generation Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Architecture Section – State Generation Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Architecture Section – State Generation (continued) Images courtesy of Addison Wesley Longman, Inc. Copyright

Architecture Section – State Generation (continued) Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Architecture Section – State Transition Images courtesy of Addison Wesley Longman, Inc. Copyright ©

Architecture Section – State Transition Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL – Low Level of Abstraction Images courtesy of Addison Wesley Longman, Inc. Copyright

VHDL – Low Level of Abstraction Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

VHDL – Advanced Capabilities • • • Components Timing Simulation Images courtesy of Addison

VHDL – Advanced Capabilities • • • Components Timing Simulation Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Summary • • • Micro-operations RTL specifications Realizing RTL specifications VHDL Images courtesy of

Summary • • • Micro-operations RTL specifications Realizing RTL specifications VHDL Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Transfer Register dan Mikrooperasi Bahasa Transfer Register 4Transfer Register dan Mikrooperasi Bahasa Transfer Register 4
Register Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONSRegister Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONS
Register Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONSRegister Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONS
Register Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONSRegister Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONS
REGISTER TRANSFER LANGUAGE RTL Outline Register Transfer LanguageREGISTER TRANSFER LANGUAGE RTL Outline Register Transfer Language
Register Transfer and Microoperations Contents Register Transfer languageRegister Transfer and Microoperations Contents Register Transfer language
Register Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONSRegister Transfer operations 1 REGISTER TRANSFER AND MICROOPERATIONS
1 REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language1 REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language
Register Transfer and Microoperations 1 Overview Register TransferRegister Transfer and Microoperations 1 Overview Register Transfer
Register transfer Notation Register transfer Notation l lRegister transfer Notation Register transfer Notation l l
Register Transfer and Microoperations 1 Overview Register TransferRegister Transfer and Microoperations 1 Overview Register Transfer
Courtesy Laura Garchar Courtesy Ball State University CourtesyCourtesy Laura Garchar Courtesy Ball State University Courtesy
Business Register in Sweden Public Register Statistical RegisterBusiness Register in Sweden Public Register Statistical Register
Lect 9 Register Continued Register A register isLect 9 Register Continued Register A register is
REGISTER REGISTER Register adalah suatu rangkaian logika yangREGISTER REGISTER Register adalah suatu rangkaian logika yang
RANGKAIAN DIGITAL SHIFT REGISTER Register Register adalah rangkaianRANGKAIAN DIGITAL SHIFT REGISTER Register Register adalah rangkaian
Register and Style Register Style Register Language choicesRegister and Style Register Style Register Language choices
CPU Register Register Register is a Group ofCPU Register Register Register is a Group of
PERTEMUAN 13 REGISTER REGISTER Register adalah suatu kelompokPERTEMUAN 13 REGISTER REGISTER Register adalah suatu kelompok
RANGKAIAN DIGITAL SHIFT REGISTER Register Register adalah rangkaianRANGKAIAN DIGITAL SHIFT REGISTER Register Register adalah rangkaian
RANGKAIAN DIGITAL SHIFT REGISTER Register Register adalah rangkaianRANGKAIAN DIGITAL SHIFT REGISTER Register Register adalah rangkaian
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languages natural languages written languages spoken languages visuallanguages natural languages written languages spoken languages visual
languages natural languages written languages spoken languages visuallanguages natural languages written languages spoken languages visual