A Short Introduction to DSP Microprocessor Architecture R

A Short Introduction to DSP Microprocessor Architecture R. C. Maher ECEN 4002/5002 DSP Laboratory Spring 2003 ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 1

What makes a DSP chip a DSP? • Conventional microprocessors use the Von Neumann architecture: program and data all in a single memory. Address and data buses are shared between instruction and data fetches. Address Memory CPU/ALU Data ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 2

• Von Neumann architecture is inexpensive, simple, and effective, BUT there are performance problems: – Von Neumann “bottleneck”: fetch for next instruction collides with data fetch/store – Buses may be idle during instruction decode – DSP algorithms often have “multiplyaccumulate” requirements: coef[n] * data[n], where two operands must be fetched • Most DSP chips use Harvard architecture: separate memory space(s) for program and data ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 3

Harvard Architecture P Address Program Memory CPU/ALU Instr. D 1 Address D 1 Data D 2 Address Data Memory #1 ECEN 4002 Spring 2003 D 2 Data #2 DSP Lab Intro R. C. Maher 4

DSP Architectural Features • ALU typically centered around Multiply. Accumulate (MAC) structure with large accumulator – Digital filters require accumulated sum-ofproducts • Multiple address generators to handle separate memory spaces – Address units handle modulo buffer arithmetic ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 5

DSP Data Representation • Numerical values represented as binary fractions: -1. 0 value < 1. 0 Radix point -20 2 -1 2 -2 2 -3 2 -(n-1) Sign bit ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 6

Why a fractional representation? • The product of two fractional numbers is also a fractional number • Normalized representation is convenient • Coefficients from digital filter designs are typically already in fractional form ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 7

DSP Architecture: Accumulator • Accumulator register holds intermediate results (nbit number x n-bit number yields 2 n-1 bit number) • Accumulator typically has extra “guard bits” or “extension register” for overflow Input Register Mult Guard ECEN 4002 Spring 2003 Accum High DSP Lab Intro Accum Low R. C. Maher 8

Accumulator Example Sign bit 28 … 21 20 2 -1 … 2 -23 2 -24 … … Guard (8 bits) Accum High (24 bits) … 2 -47 … Accum Low (24 bits) Radix point Motorola 56 xxx has two 56 -bit accumulators (48 -bit result with 8 guard bits) ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 9

Digital Filter Example • Simple FIR filter is given by • Current output is sum of product of coefficients and past input values. ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 10

Filter example (cont. ) x[n] Z-1 b 0 Z-1 b 1 Z-1 b 2 + y[n] x[n-1] x[n-2] x[n-3] ECEN 4002 Spring 2003 b 3 DSP Lab Intro R. C. Maher 11

Filter example (cont. ) • Procedure: – Clear accumulator – Fetch coefficient and data – MAC – Repeat fetch & MAC until done ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 12

DSP Support for Parallel Moves • Need to fetch next coefficient and next stored value at each step in the filter • DSPs generally support a parallel move or fetch operation while MAC is computed • This design avoids idle ALU and data buses Ex: mac x 0, y 0, a ECEN 4002 Spring 2003 x: (r 0)+, x 0 DSP Lab Intro R. C. Maher y: (r 4)+, y 0 13

Summary • DSP chips use the Harvard architecture: separate program and data memory spaces • ALU is centered around the multiply-accumulate (MAC) function • DSPs typically use a fractional number representation • Address computation generally supports modulo buffer address arithmetic • DSPs avoid idle cycles by allowing parallel actions ECEN 4002 Spring 2003 DSP Lab Intro R. C. Maher 14