16 482 16 561 Computer Architecture and Design

16. 482 / 16. 561 Computer Architecture and Design Instructor: Dr. Michael Geiger Summer 2015 Lecture 1: Course overview Introduction to computer architecture Intro to MIPS instruction set

Lecture outline n Announcements/reminders q n Course overview q q q n n HW 1 due 5/22 Instructor information Course materials Course policies Resources Course outline Introduction to computer architecture Introduction to MIPS instruction set 10/15/2021 Computer Architecture Lecture 1 2

Course staff & meeting times n Lectures: q n T/Th 1 -4 PM, Ball 313 Instructor: Dr. Michael Geiger q q E-mail: Michael_Geiger@uml. edu Phone: 978 -934 -3618 (x 43618 on campus) Office: 118 A Perry Hall Office hours: T/Th 12 -1 PM n n n 10/15/2021 Student questions are top priority during these hours Also available by appointment at other times Only on campus days we have class (T/Th + F 5/29, 6/12 only) Computer Architecture Lecture 1 3

Course materials n Textbook: q David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 5 th edition, 2013. n 10/15/2021 ISBN: 9780124077263 Computer Architecture Lecture 1 4

Additional course materials n Course websites: http: //mjgeiger. github. io/comp. Arch/sum 15/index. htm http: //mjgeiger. github. io/comp. Arch/sum 15/schedule. htm q n Will contain lecture slides, handouts, assignments Discussion group through piazza. com: q q q Allow common questions to be answered for everyone All course announcements will be posted here Will use as class mailing list—please enroll ASAP 10/15/2021 Computer Architecture Lecture 1 5

Course policies n n Prerequisites (16. 482): 16. 265 (Logic Design) and 16. 317 (Microprocessors I) Academic honesty q q q All assignments are to be done individually unless explicitly specified otherwise by the instructor Any copied solutions, whether from another student or an outside source, are subject to penalty You may discuss general topics or help one another with specific errors, but do not share assignment solutions n 10/15/2021 Must acknowledge assistance from classmate in submission Computer Architecture Lecture 1 6

Grading and exam dates n Grading breakdown q q q n Homework assignments: 55% Midterm exam: 20% Final exam: 25% Exam dates q q Midterm exam: Thursday, June 4 Final exam: Thursday, June 25 10/15/2021 Computer Architecture Lecture 1 7

Tentative course outline n n General computer architecture introduction Instruction set architecture Digital arithmetic Datapath/control design q q q n Memory hierarchy design q q n n Basic datapath Pipelining Multiple issue and instruction scheduling Caching Virtual memory Storage and I/O Multiprocessor systems 10/15/2021 Computer Architecture Lecture 1 8

What is computer architecture? n High-level description of q Computer hardware n q Interaction between software and hardware n n n Less detail than logic design, more detail than black box Look at how performance can be affected by different algorithms, code translations, and hardware designs Instruction set architecture (ISA) defines interface between hardware and software Can use to explain q q q General computation A class of computers A specific system 10/15/2021 Computer Architecture Lecture 1 9

Role of the ISA n n User writes high-level language (HLL) program Compiler converts HLL program into assembly for the particular instruction set architecture (ISA) Assembler converts assembly into machine language (bits) for that ISA Resulting machine language program is loaded into memory and run 10/15/2021 Computer Architecture Lecture 1 10

ISA design n Think about a HLL statement like X[i] = i * 2; n ISA defines how such statements are translated to machine code q What information is needed? 10/15/2021 Computer Architecture Lecture 1 11

ISA design (continued) n Questions every ISA designer must answer q How will the processor implement this statement? n n n q Where are X[i] and i located? n n q What operations are available? How many operands does each instruction use? How do we reference the operands? What types of operands are supported? How big are those operands Instruction format issues n n n 10/15/2021 How many bits per instruction? What does each bit or set of bits represent? Are all instructions the same length? Computer Architecture Lecture 1 12

Design goal: fast hardware n From ISA perspective, must understand how processor executes instruction q q Fetch the instruction from memory Decode the instruction n q q Determine operation Determine addresses for operands Fetch operands Execute instruction Store result (and go back to step 1 … ) 10/15/2021 Computer Architecture Lecture 1 13

MIPS: A "Typical" RISC ISA n n 32 -bit fixed format instruction (3 formats) Registers q 32 32 -bit integer GPRs (R 1 -R 31, R 0 always = 0) n q 32 32 -bit floating-point GPRs (F 0 -F 31) n n n Depending on MIPS version, may refer to regs using $ + number (i. e. , $1, $2) or mnemonic ($t 1, $s 0) For double-precision FP, registers paired 3 -address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement Simple branch conditions Delayed branch 10/15/2021 Computer Architecture Lecture 1 14

Operands n Example: load-store instructions of form: LOAD R 2, C ADD R 3, R 1, R 2 STORE R 3, A n Three general classes of operands q Immediate operands: encoded directly in instruction n q Register operands: register number encoded in instruction, register holds data n q Example: ADDI R 3, R 1, 25 Example: R 1, R 2, and R 3 in above code sequence Memory operands: address encoded in instruction, data stored in memory n n 10/15/2021 Example: A and C in above code sequence In load-store processor, can’t directly operate on these data Computer Architecture Lecture 1 15

Memory operands n Specifying addresses is not straightforward q n Length of address usually = length of instruction Addressing modes: different ways of specifying operand location q Already discussed two n n q Immediate: operand encoded directly in instruction Register direct: operand in register, register # in instruction For values in memory, use effective address n n Parts of address specified in instruction; address actually calculated as part of execution Common EA mode: base + displacement q q 10/15/2021 Base register + constant displacement MIPS example: lw $1, 10($2) EA = 10 + (contents of $2) Computer Architecture Lecture 1 16

MIPS instruction formats n n All fixed length (32 -bit) instructions Register instructions: R-type 31 26 25 op n 20 rs 16 15 rt 11 rd 10 6 shamt 5 0 funct Immediate instructions: I-type 31 26 25 op n 21 21 rs 20 16 15 rt 0 immediate/address Jump instructions: J-type 31 26 op 10/15/2021 25 0 target (address) Computer Architecture Lecture 1 17

MIPS addressing modes n Immediate addressing q n Register addressing q n Example: addi $t 0, $t 1, 150 Example: sub $t 0, $t 1, $t 2 Base addressing (base + displacement) q Example: lw $t 0, 16($t 1) 10/15/2021 Computer Architecture Lecture 1 18

MIPS integer registers Name Register number $zero 0 Usage Constant value 0 $v 0 -$v 1 2 -3 Values for results and expression evaluation $a 0 -$a 3 4 -7 Function arguments $t 0 -$t 7 8 -15 Temporary registers $s 0 -$s 7 16 -23 Callee save registers $t 8 -$t 9 24 -25 Temporary registers $gp 28 Global pointer $sp 29 Stack pointer $fp 30 Frame pointer $ra 31 Return address n List gives mnemonics used in assembly code q n Can also directly reference by number ($0, $1, etc. ) Conventions q q q 10/15/2021 $s 0 -$s 7 are preserved on a function call (callee save) Register 1 ($at) reserved for assembler Registers 26 -27 ($k 0 -$k 1) reserved for operating system Computer Architecture Lecture 1 19

Computations in MIPS n n All computations occur on full 32 bit words Computations use signed (2’s complement) or unsigned operands (positive numbers) q Example: 1111 1111 is – 1 as a signed number and 4, 294, 967, 294 as an unsigned number Operands are in registers or are immediates Immediate (constant) values are only 16 bits q 32 -bit instruction must also hold opcode, source and destination register numbers q Value is sign extended before usage to 32 bits q Example: 1000 0000 becomes 1111 1000 0000 10/15/2021 Computer Architecture Lecture 1 20

MIPS instruction categories n Data transfer instructions q q n Computational instructions (arithmetic/logical) q q n Example: lw, sb Always I-type Examples: add, and, sll Can be R-type or I-type Control instructions q q Example: beq, jr Any of the three formats (R-type, I-type, J-type) 10/15/2021 Computer Architecture Lecture 1 21

MIPS data transfer instructions n Memory operands can be bytes, half-words (2 bytes), or words (4 bytes [32 bits]) q n opcode determines the operand size Half-word and word addresses must be aligned q q q Divisible by number of bytes being accessed Bit 0 must be zero for half-word accesses Bits 0 and 1 must be zero for word accesses Byte address Aligned word 0 4 8 12 Unaligned half-word 16 20 10/15/2021 Aligned half-word Computer Architecture Lecture 1 Unaligned word 22

Byte order (“endianness”) n n In a multi-byte operand, how are the bytes ordered in memory? Assume the value 1, 000 (0 x. F 4240) is stored at address 80 q In a big-endian ISA (like MIPS), the most significant byte (the “big” end) is at address 80 00 0 F 42 40 … 79 80 81 82 83 84 … q In a little-endian ISA (like x 86), it’s the other way around 40 42 0 F 00 … 79 80 81 82 83 84 … 10/15/2021 Computer Architecture Lecture 1 23

MIPS data transfer instructions n(cont. ) For all cases, calculate effective address first q n lb, lh, lw q q n Get data from addressed memory location Sign extend if lb or lh, load into rt lbu, lhu, lwu q q n Flat memory model EA = address being accessed Get data from addressed memory location Zero extend if lb or lh, load into rt sb, sh, sw q Store data from rt (partial if sb or sh) into addressed location 10/15/2021 Computer Architecture Lecture 1 24

Data transfer examples n n Say memory holds the word 0 x. ABCD 1234, starting at address 0 x 1000, $t 0 holds the value 0 x 1000, and $s 0 holds 0 x. DEADBEEF What are the results of the following instructions? q q q lh $t 1, 2($t 0) lb $t 2, 1($t 0) lbu $t 3, 0($t 0) sh $s 0, 0($t 0) sb $s 0, 3($t 0) 10/15/2021 Computer Architecture Lecture 1 25

Solutions to examples n If mem[0 x 1000] = 0 x. ABCD 1234, $t 0 holds the value 0 x 1000, and $s 0 holds 0 x. DEADBEEF q lh $t 1, 2($t 0) n q lb $t 2, 1($t 0) n q $t 3 = mem[0 x 1000] = 0 x 000000 AB sh $s 0, 0($t 0) n n q $t 2 = mem[0 x 1001] = 0 x. FFFFFFCD lbu $t 3, 0($t 0) n q $t 1 = mem[0 x 1002] = 0 x 00001234 Change 16 bits at address 0 x 1000 mem[0 x 1000] = 0 x. BEEF 1234 sb $s 0, 3($t 0) n n 10/15/2021 Change 8 bits at address 0 x 1003 mem[0 x 1000] = 0 x. ABCD 12 EF Computer Architecture Lecture 1 26

MIPS computational instructions n Arithmetic q q Signed: add, sub, mult, div Unsigned: addu, subu, multu, divu n q Immediate: addi, addiu n n Immediates are sign-extended (why? ) Logical q q and, or, nor, xor andi, ori, xori n n Ignores overflow but still uses signed value Immediates are zero-extended (why? ) Shift (logical and arithmetic) q srl, sll – shift right (left) logical n n n q Shift the value in rs by shamt digits to right or left Fill empty positions with 0 s Store the result in rd sra – shift right arithmetic n 10/15/2021 Same as above, but sign-extend the high-order bits Computer Architecture Lecture 1 27

MIPS computational instructions (cont. ) n Set less than q Used to evaluate conditions n q slt, sltu (Format: slt rd, rs, rt) n q Condition is rs < rt slti, sltiu (Format: slti rd, rs, immediate) n n n Set rd to 1 if condition is met, set to 0 otherwise Condition is rs < immediate Immediate is sign-extended Load upper immediate (lui) q Shift immediate 16 bits left, append 16 zeros to right, put 32 -bit result into rd 10/15/2021 Computer Architecture Lecture 1 28

Examples of arithmetic instructions Instruction Meaning add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 3 registers; signed addition sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 3 registers; signed subtraction addu $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 3 registers; unsigned addition addi $s 1, $s 2, 50 $s 1 = $s 2 + 50 2 registers and immediate; signed addiu $s 1, $s 2, 50 $s 1 = $s 2 + 50 2 registers and immediate; unsigned 10/15/2021 Computer Architecture Lecture 1 29

Examples of logical instructions Instruction Meaning and $s 1, $s 2, $s 3 $s 1 = $s 2 & $s 3 3 registers; logical AND or $s 1, $s 2, $s 3 $s 1 = $s 2 | $s 3 3 registers; logical OR xor $s 1, $s 2, $s 3 $s 1 = $s 2 �$s 3 3 registers; logical XOR nor $s 1, $s 2, $s 3 $s 1 = ~($s 2 + $s 3) 3 registers; logical NOR 10/15/2021 Computer Architecture Lecture 1 30

Computational instruction examples n Say $t 0 = 0 x 00000001, $t 1 = 0 x 00000004, n $t 2 = 0 x. FFFF What are the results of the following instructions? q q q sub $t 3, $t 1, $t 0 addi $t 4, $t 1, 0 x. FFFF andi $t 5, $t 2, 0 x. FFFF sll $t 6, $t 0, 5 slt $t 7, $t 0, $t 1 lui $t 8, 0 x 1234 10/15/2021 Computer Architecture Lecture 1 31

Solutions to examples n If $t 0 = 0 x 00000001, $t 1 = 0 x 00000004, $t 2 = 0 x. FFFF q sub $t 3, $t 1, $t 0 n q addi $t 4, $t 1, 0 x. FFFF n q $t 6 = 0 x 00000001 << 5 = 0 x 00000020 slt $t 7, $t 0, $t 1 n n q $t 5 = 0 x. FFFF AND 0 x 0000 FFFF = 0 x 0000 FFFF sll $t 6, $t 0, 5 n q $t 4 = 0 x 00000004 + 0 x. FFFF = 0 x 00000003 andi $t 5, $t 2, 0 x. FFFF n q $t 3 = 0 x 00000004 – 0 x 00000001 = 0 x 00000003 $t 7 = 1 if ($t 0 < $t 1) $t 0 = 0 x 00000001, $t 1 = 0 x 00000004 $t 7 = 1 lui $t 8, 0 x 1234 n 10/15/2021 $t 8 = 0 x 1234 << 16 = 0 x 12340000 Computer Architecture Lecture 1 32

MIPS control instructions n Branch instructions test a condition q Equality or inequality of rs and rt n n q Value of rs relative to rt n n beq, bne Often coupled with slt, sltu, sltiu Pseudoinstructions: blt, bgt, ble, bge Target address add sign extended immediate to the PC q Since all instructions are words, immediate is shifted left two bits before being sign extended 10/15/2021 Computer Architecture Lecture 1 33

Pseudoinstructions n Assembler recognizes “instructions” that aren’t in MIPS ISA q q q n Common ops implemented using 1 -2 simple instructions Makes code writing easier Example: MIPS only has beq, bne instructions, but assembler recognizes bgt, bge, blt, ble Assembler converts pseudoinstruction into actual instruction(s) q q If extra register needed, use $at Example: bgt $t 0, $t 1, label slt $at, $t 1, $t 0 bne $at, $zero, label 10/15/2021 Computer Architecture Lecture 1 34

MIPS control instructions (cont. ) n Jump instructions unconditionally branch to the address formed by either q Shifting left the 26 -bit target two bits and combining it with the 4 high-order PC bits n q The contents of register $rs n n j jr Branch-and-link and jump-and-link instructions also save the address of the next instruction into $ra q q q 10/15/2021 jal Used for subroutine calls jr $ra used to return from a subroutine Computer Architecture Lecture 1 35

Final notes n Following slides give a few more detailed instruction examples, if you’re interested n Next time: q n Digital arithmetic Announcements/reminders: q q Sign up for the course discussion group on Piazza! HW 1 to be posted; due 5/22 10/15/2021 Computer Architecture Lecture 1 36

More data transfer examples n n If A is an array of words and the starting address of A (memory address of A[0]) is in $s 4, perform the operation: A[3] = A[0] + A[1] - A[2] Solution: lw $s 1, 0($s 4) # A[0] into $s 1 lw $s 2, 4($s 4) # A[1] into $s 2 add $s 1, $s 2 # A[0]+A[1] into $s 1 lw $s 2, 8($s 4) # A[2] into $s 2 sub $s 1, $s 2 # A[0]+A[1]-A[2] into $s 1 sw $s 1, 12($s 4) # store result in A[3] 10/15/2021 Computer Architecture Lecture 1 37

Compiling If Statements n C code: if (i==j) f = g+h; else f = g-h; q n f, g, … in $s 0, $s 1, … Compiled MIPS code: bne add j Else: sub Exit: … $s 3, $s 4, Else $s 0, $s 1, $s 2 Exit $s 0, $s 1, $s 2 Assembler calculates addresses 10/15/2021 Computer Architecture Lecture 1 38

Compiling Loop Statements n C code: while (save[i] == k) i += 1; q n i in $s 3, k in $s 5, address of save in $s 6 Compiled MIPS code: Loop: sll add lw bne addi j Exit: … 10/15/2021 $t 1, $t 0, $s 3, Loop $s 3, 2 $t 1, $s 6 0($t 1) $s 5, Exit $s 3, 1 Computer Architecture Lecture 1 39