State Machine Implementation 1022008 ECE 561 Lecture 5

State Machine Implementation 10/2/2008 ECE 561 - Lecture 5 1

Lecture Overview • Another Example – a counting machine • Another Example – Tail light controller 10/2/2008 ECE 561 - Lecture 5 2

Counting Machine • “Design a clocked synchronous state machine with two inputs, X and Y, and one output Z. The output should be 1 inputs on X and Y since reset is a multiple of 4, and 0 otherwise. • There are 4 states 10/2/2008 ECE 561 - Lecture 5 3

Construct a state table • From word description construct a state table for the problem. 10/2/2008 ECE 561 - Lecture 5 4

Do a state assignment • Having state table pick a state assignment • From here we can generate the excitation equations 10/2/0810/2/2008 ECE 561 - Lecture 5 5

Excitation Equations • D 1 = Q 2 X’ Y + Q 1’ X Y + Q 1 X’ Y’ + Q 2 X Y’ • Z = Q 1’ Q 2’ • D 2 = Q 1’ X’ Y + Q 1’ X Y’ + Q 2 X’ Y’ + Q 2 X Y 10/2/0810/2/2008 ECE 561 - Lecture 5 6

Another Example • Design a clocked synchronous state machine with one input X and two outputs, UNLK and HINT. The UNLK output should be 1 if and only if X is 0 and the sequence of inputs received on X the preceding seven clock ticks was 0110111. The HINT output should be 1 if and only if the current value of X is the correct one to move the machine close to being in the “unlocked” state (with UNLK = 1). 10/2/0810/2/2008 ECE 561 - Lecture 5 7

Create State Table • Create a state table from the word description 10/2/0810/2/2008 ECE 561 - Lecture 5 8

Choose a state assignment • To get transition/excitation table 10/2/0810/2/2008 ECE 561 - Lecture 5 9

Can use Karnaugh Map to get excitation equations • D 1 = Q 1 Q 2’ X + Q 1’ Q 2 Q 3 X’ + Q 1 Q 2 Q 3’ • D 2 = Q 2’ Q 3 X + Q 2 Q 3’ X • D 3 = Q 1 Q 2’ Q 3’ + Q 1 Q 3 X’ + Q 2’ X’. . + Q 3’ Q 1’ X’ + Q 2 Q 3’ X • UNLK = Q 1 Q 2 Q 3 X’ • HINT = Q 1’ Q 2’ Q 3’ X’ + Q 1 Q 2’ X + Q 2’ Q 3 X + Q 2 Q 3 X’ + Q 2 Q 3’ X 10/2/0810/2/2008 ECE 561 - Lecture 5 . . 10

For both examples • Having the excitation and output equation can do the implementation in discrete logic or perform a schematic capture for FPGA tools such as XILINX or Altera. 10/2/0810/2/2008 ECE 561 - Lecture 5 11

Another example • This is a example of a “real” deisgn • The T-Bird Tail Light Problem 10/2/0810/2/2008 ECE 561 - Lecture 5 12

The Transistion Table • Can again get the transition table 10/2/0810/2/2008 ECE 561 - Lecture 5 13

The State Diagram • Can also draw a state diagram 10/2/0810/2/2008 ECE 561 - Lecture 5 14

Final steps • Choose F/F type • Choose a state assignment • Develop the transition/excitation table for that state assignment • Generate the equations 10/2/0810/2/2008 ECE 561 - Lecture 5 15

Assignment 3 • Carry through the remaining steps to get implementation and output equations and the circuit diagram for an implementation for the following state table. 10/2/0810/2/2008 ECE 561 - Lecture 5 16