VLSI Testing Lecture 11 BIST n n n
VLSI Testing Lecture 11: BIST n n n Copyright 2005, Agrawal & Bushnell Definition of BIST Pattern generator n LFSR Response analyzer n MISR n Aliasing probability BIST architectures n Test per scan n Test per clock n Circular self-test n Memory BIST Summary Lecture 13: BIST 1
Define Built-In Self-Test n Implement the function of automatic test equipment (ATE) on circuit under test (CUT). Hardware added to CUT: n n n Pattern generation (PG) Response analysis (RA) Test controller Stored Test Patterns CK Pin Electronics CUT Test control HW/SW Stored responses Comparator hardware ATE Copyright 2005, Agrawal & Bushnell BIST Enable Test control logic n PG CUT RA Go/No-go signature Lecture 13: BIST 2
Pattern Generator (PG) n n n RAM or ROM with stored deterministic patterns Counter Pseudorandom pattern generator n Feedback shift register n Cellular automata Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 3
Pseudorandom Integers Xk = Xk-1 + 3 (modulo 8) Xk = Xk-1 + 2 (modulo 8) 0 7 0 1 7 2 Start 6 1 2 Start 6 +3 5 +2 3 5 4 3 4 Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2. . . Sequence: 2, 4, 6, 0, 2. . . Maximum length sequence: 3 and 8 are relative primes. Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 4
Pseudo-Random Pattern Generation n Standard Linear Feedback Shift Register (LFSR) § Produces patterns algorithmically – repeatable § Has most of desirable random # properties May not cover all 2 n input combinations Long sequences needed for good fault coverage Copyright 2005, Agrawal & Bushnell either hi = 0, i. e. , XOR is deleted or hi = Xi Initial state (seed): X 0, X 1, . . . , Xn-1 must not be 0, 0, . . . , 0 Lecture 13: BIST 5
Matrix Equation for Standard LFSR X 0 (t + 1) X 1 (t + 1). . . Xn-3 (t + 1) Xn-2 (t + 1) Xn-1 (t + 1) = X (t + 1) = Ts X (t) Copyright 2005, Agrawal & Bushnell 0 0. . . 0 0 1 1 0. . . 0 0 h 1 0 1. . . 0 0 h 2 … … 0 0. . . 1 0 0 0. . . 0 1 … … … hn-2 hn-1 X 0 (t) X 1 (t). . . Xn-3 (t) Xn-2 (t) Xn-1 (t) (Ts is companion matrix) Lecture 13: BIST 6
LFSR Implements a Galois Field § § n Galois field (mathematical system): § Multiplication by X same as right shift of LFSR § Addition operator is XOR ( Å ) Ts companion matrix: § 1 st column 0, except nth element which is always 1 (X 0 always feeds back) § Rest of row n – feedback coefficients h i § Remaining identity matrix means a right shift Near-exhaustive (maximal length) LFSR n § Cycles through 2 – 1 states (excluding all-0) Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 7
LFSR Properties n Must not initialize to all 0’s – hangs n If X is initial state, LFSR progresses through states X, Ts 2 X, Ts 3 X, … n Matrix period: Smallest k such that Tsk = I § § § n k = LFSR cycle length Maximum length k = 2 n-1, when feedback (characteristic) polynomial is primitive Example: 1 + X+ X 3 Characteristic polynomial: 1 + h 1 x + h 2 X 2 + … + hn-1 Xn-1 + Xn Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 8
LFSR: 1 + X 3 RESET 100 001 000 D Q X 2 D Q X 1 010 110 D Q X 0 101 111 011 CK RESET X 2 X 1 X 0 Test of primitiveness: Characteristic polynomial of degree n must divide 1 + Xq for q = n, but not for q < n Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 9
LFSR as Response Analyzer n n Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial CRCC divides the PO polynomial by its characteristic polynomial § Leaves remainder of division in LFSR § Must initialize LFSR to seed value (usually 0) before testing After testing – compare signature in LFSR to precomputed signature of fault-free circuit Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 10
Example Modular LFSR Response Analyzer n LFSR seed is “ 00000” Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 11
Signature by Logic Simulation Input bits X 0 X 1 Initial State 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 Copyright 2005, Agrawal & Bushnell X 2 0 0 0 1 Lecture 13: BIST X 3 0 0 1 0 1 X 4 0 0 0 1 0 Signature 12
Signature by Polynomial Division Input bit stream: 0 1 0 0 0 1 0 ∙ X 0 + 1 ∙ X 1 + 0 ∙ X 2 + 1 ∙ X 3 + 0 ∙ X 4 + 0 ∙ X 5 + 0 ∙ X 6 + 1 ∙ X 7 X 2 + 1 X 5 + X 3 + X + 1 + X 3 +X X 7 Char. polynomial X 7 + X 5 + X 3 + X 2 + X X 5 + X 3 + X 2 remainder +X +1 +1 Signature: X 0 X 1 X 2 X 3 X 4 = 1 0 1 1 0 Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 13
Multiple-Input Signature Register (MISR) n n Problem with ordinary LFSR response compacter: § Too much hardware if one of these is put on each primary output (PO) Solution: MISR – compacts all outputs into one LFSR § Works because LFSR is linear – obeys superposition principle § Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 14
Modular MISR Example X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) = Copyright 2005, Agrawal & Bushnell 0 0 1 1 0 1 0 Lecture 13: BIST X 0 (t) X 1 (t) X 2 (t) + d 0 (t) d 1 (t) d 2 (t) 15
Aliasing Probability n n Aliasing means that faulty signature matches faultfree signature Aliasing probability ~ 2 -n n where n = length of signature register n Example 1: n = 4, Aliasing probability = 6. 25% n Example 2: n = 8, Aliasing probability = 0. 39% n Example 3: n = 16, Aliasing probability = 0. 0015% Fault-free signature Copyright 2005, Agrawal & Bushnell 2 n-1 faulty signatures Lecture 13: BIST 16
BIST Architectures n n Copyright 2005, Agrawal & Bushnell Test per scan Test per clock Circular self-test Memory BIST Lecture 13: BIST 17
Test Per Scan BIST PG Scan register Comb. logic PI and PO disabled during test Scan register BIST enable BIST Control logic Go/No-go signature Comb. logic Scan register Comb. logic RA Copyright 2005, Agrawal & Bushnell Scan register Lecture 13: BIST 18
Test per Clock BIST n New fault set tested every clock period n Shortest possible pattern length § 10 million BIST vectors, 200 MHz test / clock § Test Time = 10, 000 / 200 x 106 = 0. 05 s § Shorter fault simulation time than test / scan Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 19
Circular Self Test Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 20
Built-in Logic Block Observer (BILBO) n Combined functionality of D flip-flop, pattern generator, response analyzer, and scan chain § Reset all FFs to 0 by scanning in zeros Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 21
Test per Clock with BILBO n SI – Scan In n SO – Scan Out n Characteristic polynomial: 1 + x + … + xn n CUTs A and C: BILBO 1 is MISR, BILBO 2 is LFSR n CUT B: BILBO 1 is LFSR, BILBO 2 is MISR Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 22
BILBO Serial Scan Mode n B 1 B 2 = “ 00” n Dark lines show enabled data paths Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 23
BILBO LFSR Pattern Generator Mode n B 1 B 2 = “ 01” Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 24
BILBO in DFF (Normal) Mode n B 1 B 2 = “ 10” Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 25
BILBO in MISR Mode n B 1 B 2 = “ 11” Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 26
Memory BIST Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 27
Summary n n n LFSR pattern generator and MISR response analyzer – preferred BIST methods BIST has overheads: test controller, extra circuit delay, primary input MUX, pattern generator, response compacter, DFT to initialize circuit and test the test hardware BIST benefits: § At-speed testing for delay and stuck-at faults § Drastic ATE cost reduction § Field test capability § Faster diagnosis during system test § Less effort in the design of testing process § Shorter test application times Copyright 2005, Agrawal & Bushnell Lecture 13: BIST 28
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