Phase Locked Loops Ref PFD Loop Filter VCO
- Slides: 14
Phase Locked Loops Ref PFD Loop Filter VCO 1/N LO f. LO=fref*N/M Once locked, f_ref = f_div But f_div = f_LO / N Therefor, f_LO = N * f_ref. Smallest change in f_LO is f_ref. For high tuning resolution, need very small f_ref. 1
Conflict between freq resolution and PLL bandwidth / settling time • Since PFD is controlled by f_ref, hence f_sampling = f_ref • For stability and transfer characteristics, need f_ref to be 10’s of times of PLL bandwidth • Hence, f_BW ~ 0. 01 to 0. 1 * f_ref • PLL settling time = k * 1/_BW 2
Increasing freq resolution and BW Ref 1/M PFD Loop Filter 1/N VCO LO f. LO=fref*N/M Phase. Locked Loop After lock, PFD input signals have the same freq. Hence, f_ref / M = f_LO / N Therefor, f_LO = f_ref *N/M Freq resolution: f_ref * (N 1/M 1 –N 2/M 2) PFD sampling freq: f_sampling = f_ref / M PLL bandwidth: 0. 02 to 0. 05 * f_ref / M 3
Phase Locked Loops Ref PFD Loop Filter VCO LO 1/N dither N N 1 N = N 1 + dither In lock, f_LO = average(N) * f_ref. Smallest change in f_LO can be very fine. 4
Phase Locked Loops Ref PFD dither N_frac Loop Filter VCO LO 1/N Carry out Accumulator Smallest increments in N_frac sets freq resolution. Problem: periodic errors. 5
For N = 4. 25, user integer 4 and N_frac = 0. 25 In every 4 cycles, div by 4 three times and div by 5 once When carry signal is generated, “swallow” one VCO cycle Notice the periodic error signal that feed into fileter 6
Accumulator Operation • Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value • Accumulator residue corresponds to instantaneous phase error – Increments by the fractional value input into the accumulator 7
Phase Locked Loops Ref PFD dither N_sd Loop Filter VCO LO 1/N Sigma-Delta modulator N = N or N+1 Riley US Patent 4965531, 1989; JSSC ‘ 93 MASH Noise shaping. Removes periodic tones. 8
The amount of noise depends on PLL band width. Smaller BW lower noise 9
Divider • At high frequency, divider block is challenging to design • It consumes a lot of power • Typically implemented using several stages • Can have each stage operating at gradually lower freq to save power 10
Divide-by-2 Circuit • Achieves frequency division by clocking two latches (i. e. , a register) in negative feedback • Latches may be implemented in various ways according to speed/power requirements 11
• Advantages – Reasonably fast, compact size – No static power dissipation, differential clock not required • Disadvantages – Slowed down by stacked PMOS, signals goes through three gates per cycle – Requires full swing input clock signal 12
• Very fast due to small swing and absence of PMOS devices – Additional speedup can be obtained by using inductors • High power, large area • Differential signals required, Biasing sources required 13
Divide by 2 or 3 • Normal mode of operation: CON*= 0 ⇒Y = 0 – Register B acts as divide-by-2 circuit • Divide-by-3 operation: CON*= 1 ⇒Y = 1 – Reg. B remains high for an extra cycle – Causes Y to be set back to 0 ⇒Reg. B toggles again – CON* must be set back to 0 before Reg. B toggles to prevent extra pulses from being swallowed 14
