FM Transmitter FM Modulation using VCO fout 1

FM Transmitter

FM Modulation using VCO fout [1] Vin - Free Running Frequency of VCO Corresponding DC bias - Gain of VCO

Block Diagram Input DC Bias Vcc/2 VCO PA

Chipset • 4046 Phase-Locked Loop • LM 7171 Wide-Band Power Amplifier • 741 Op Amp

4046 PLL Only use the VCO

4046 VCO Characteristic C 1>=100 p. F

Schematic

PCB Layout Considerations • The signal traces should be short and wide to lower the impedance. • The width of the signal traces has to satisfy current driving capacity. • Any used board area should be shorted to ground to reduce AC noise. • Sockets and pads will induce extra capacitance, so components should be directly soldered to board. • Surface mount components are preferred over discrete ones for less lead inductance.

PCB Layout

Measured Results • Carrier Frequency: 15 MHz • Bandwidth: Controllable • Output Power: 500 m. W

FM Receiver

FM Demodulation using PLL [2] in PFD LF VCO Ve

Loop Filter Design [3]

VCO Design • VCO free running frequency = Carrier Frequency • VCO Frequency Range is no smaller than Bandwidth • Large VCO gain will increase PLL natural frequency n and thus improves PLL tracking capability

Block Diagram BPF LNA PFD LF VCO Amp

Chipset • 4046 PLL • CLC 425 Wide-band LNA

4046 PLL

Schematic

PCB Layout

Superheterodyne FM Receiver

Block Diagram Input Matching Mixer IF Amp + IF Filter LO FM Demodulator Amp

Chipset • TDA 7000 – FM Radio • LM 3875 – Audio Power Amplifier

TDA 7000 [4]

IF Filter

Quadrature Demodulator Vout fin

IF Harmonic Distortion IF=70 k. Hz

IF Distortion Suppression FLL

Correlator To suppress interstation noise • Not Modulated • Lightly Modulated • Heavily Modulated

Schematic

PCB Layout

Monolithic FSK Transmitter [5]

Block Diagram PLL Reference Frequency Dual Modulus Prescaler Digital Input Analog Input A/D Converter Shift Register Clock Data Sampling Rate Output

Inverter

NAND – 2 Input

NAND – 3 Input

NAND – 4 Input

NOR – 2 Input

XOR

Transmission Gate

Edge-Triggered D Flip-Flop

D Flip-Flop with ‘CLEAR’

Voltage Comparator

8 -to-3 Encoder

A/D Converter

Parallel-Serial Shift Register

Phase-Frequency Detector

VCO

Dual Modulus Prescaler [6]

Output Driver To drive capacitive load with minimum delay

Capacitor Driving Capability CL=100 p f=50 MHz

Synthesizer

Synthesizer Response

ADC and SR Response

Chip Layout

Digital Switching Noise [7]

Noise Mechanism • Digital switching injects current into substrate through various kinds of capacitance, which propagates through the substrate and affects analog circuits. • Digital switching draws current from power supply rail with impedance and thus creates voltage drop on power supply rail.

Digital Switching Noise in PLL • PLL is a typical mixed-signal integrated circuit PFD LF VCO Noise Coupling /N

Simulation Results Error Voltage VCO output

Noise Reducing Techniques • Use Differential Topology • Separate Power Supply Rails • Use guard rings • Multi-chip Module • Heterogeneous integration

Test Structure 1 PFD LF VCO /N All building blocks share power supply rails

Chip Layout 1

Test Structure 2 PFD LF VCO /N The counter uses separate power supply rails

Chip Layout 2

Test Structure 3 PFD LF VCO /N • The counter uses separate power supply rails • The PFD and VCO are shielded and ring guarded

Guard Ring p+ Sink the coupling P-type Substrate p+

On-Chip Shielding Metal 3 Via 2 Via 1 Contact Ohmic Contact ICs Radiation

Chip Layout 3

Test Structure 4 PFD LF VCO /N • The counter uses separate power supply rails • Use guard rings around PFD and VCO • Implement LC VCO

LC VCO Lower Phase Noise than Ring Oscillator

Oscillator Basics • Positive feedback of 2 n phase shift • Unity loop gain - Tank Loss • Phase noise is reverse proportional to Q [8]

Chip Layout

Electromagnetic Coupling

Microstrip Line Coupling 4 3 L W 1 S 2 [9]

Electric Field Distribution Even Mode Odd Mode

Impedance Matrix Zoe - even mode characteristic impedance Zoo - odd mode characteristic impedance - propagation constant

Different Configurations Low Pass Band Pass

Experiment Setup

Results The coupling depends on L, W, S, and

Integrated Inductor Coupling • Coupling between integrated spiral inductors • Coupling from spiral inductors to transistors [10]

2. 5 D Integrated Inductor [11]

Interference Effects on PLL Performance [12]

References 1. 2. 3. 4. 5. Jerry D. Gibson, Principles of Digital and Analog Communications Floyd M. Gardner, Phaselock Techniques Roland E. Best, Phase-Locked Loops – Theory, Design, and Applications W. H. A. Van Dooremolen and M. Hufschmidt, A complete FM radio on a chip R. Jacob Baker, Harry W. Li, David E. Boyce, CMOS Circuit Design, Layout, and Simulation 6. J. Navarro Soares and W. A. M. Van Noije, A 1. 6 -GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique, IEEE Journal of SSCC, Vol. 34, No. 1, Jan 1999 7. Patrik Larsson, Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise, IEEE Journal of SSCC, Vol. 36, No. 7, July 2001 8. Dan H. Wolaver, Phase-Locked Loop Circuit Design 9. E. M. T. Jones and J. T. Bolljahn, Coupled-Strip-Transmission-Line Filters and Directional Couplers, IRE Trans on Microwave Theory and Techniques, 1956 10. A. O. Adan, M. Fukumi, K. Higashi, T. Suyama, M. Miyamoto, M. Hayashi, Electromagnetic Coupling Effects in RFCOMS Circuits, 2002 IEEE MTT-S Digest 11. Jaime Aguilera and Joaquin De No, A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Application 12. Murat F. Karsi, William C. Lindsey, Effects of CW Interference on Phase-Locked Loop Performance, IEEE Trans on Comm, Vol. 48, No. 5, May 2000