Flip Flops Not a gymnastic movement 91509 L

  • Slides: 15
Download presentation
Flip Flops Not a gymnastic movement. 9/15/09 - L 20 Flip Flops Copyright 2009

Flip Flops Not a gymnastic movement. 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 1

Class 20 – Flip Flops o o Definitions Latches n n o Set-Reset –

Class 20 – Flip Flops o o Definitions Latches n n o Set-Reset – SR The D Latch Material from section 5 -3 of text 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 2

Triggers o o o When the control input to a flip-flop changes value the

Triggers o o o When the control input to a flip-flop changes value the state of the latch in the flip-flop will change state. In a D-latch when the control input is a ‘ 1’, any changes on the input D will propagate to the output with the value of D at the time the control transitions from ‘ 1’ the final stored value. In a D flip-flop, the value on D on the rising edge (falling edge) of the control input will be the captured value. 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 3

Flip-flops o o o Constructed in such a way that they are edgetriggered. This

Flip-flops o o o Constructed in such a way that they are edgetriggered. This is in contrast to latches which are level sensitive and said to be transparent. There are two general methodologies for making flip-flops n n Edge-triggered Master-Slave 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 4

Master Slave Flip-flops o The Master-Slave SR Flip-flop o And its operation 9/15/09 -

Master Slave Flip-flops o The Master-Slave SR Flip-flop o And its operation 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 5

Master Slave D Flip-flop o o Can be constructed from the MS SR FF

Master Slave D Flip-flop o o Can be constructed from the MS SR FF by replacing the master SR latch by a D latch. This arrangement is also negative edge triggered. 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 6

A HDL model of the same o The SR latch model with control input

A HDL model of the same o The SR latch model with control input C 9/15/09 - L 20 Flip Flops ENTITY SR_latch IS PORT (S, R, C : IN BIT; Q, Q_bar : OUT BIT); END SR_latch; ARCHITECTURE one OF SR_latch IS SIGNAL CS, CR : BIT; SIGNAL Q_int, Q_bar_int : BIT; BEGIN CS <= S nand C after 1 ns; CR <= R nand C after 1 ns; Q_int <= CS nand Q_bar_int after 1 ns; Q_bar_int <= CR nand Q_int after 1 ns; Q <= Q_int; Q_bar <= Q_bar_int; END one; Copyright 2009 - Joanne De. Groat, ECE, OSU 7

A testbench to provide stimulus o o tb model Links in the latch in

A testbench to provide stimulus o o tb model Links in the latch in a master slave manner 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 8

VHDL simulation results o Waveform display 9/15/09 - L 20 Flip Flops Copyright 2009

VHDL simulation results o Waveform display 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 9

The D Flip-flop o The D can be constructed from the use of a

The D Flip-flop o The D can be constructed from the use of a D latch and an SR latch. 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 10

For a positive edge FF o Add an inverter to the clock input 9/15/09

For a positive edge FF o Add an inverter to the clock input 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 11

HDL model and simulation o A HDL model of the D latch was written.

HDL model and simulation o A HDL model of the D latch was written. 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 12

HDL simulation o o Results now for the D F/F Remember the delays 9/15/09

HDL simulation o o Results now for the D F/F Remember the delays 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 13

Flip flop with preset and clear o o Allows direct setting of state of

Flip flop with preset and clear o o Allows direct setting of state of flip-flop. When initially powered state of flip-flop is unknown. The sets the FF to a known state. 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 14

Class 20 assignment o o Covered sections 5 -1 and 5 -2 Problems for

Class 20 assignment o o Covered sections 5 -1 and 5 -2 Problems for hand in n o Problems for practice n o L 20 HW (on webpage) none Reading for next class: sections 5 -4 9/15/09 - L 20 Flip Flops Copyright 2009 - Joanne De. Groat, ECE, OSU 15

Flip Flops Sequential Logic Devices w Flip FlopsFlip Flops Sequential Logic Devices w Flip Flops
Sequential Circuits Flip Flops 1 Flip Flops ASequential Circuits Flip Flops 1 Flip Flops A
Flip Flops Flip Flops Flipflops serve as theFlip Flops Flip Flops Flipflops serve as the
Flip Flops Unit4 Flip Flop A basic sequentialFlip Flops Unit4 Flip Flop A basic sequential
40 Tera Flops Peak 35 Tera Flops Linpack40 Tera Flops Peak 35 Tera Flops Linpack
Synchronous Sequential Logic Chapter 5 Other Flip FlopsSynchronous Sequential Logic Chapter 5 Other Flip Flops
Latches and Flip Flops Latches A latch isLatches and Flip Flops Latches A latch is
FLIP FLOPS Department of IT Sarita Nahak LectFLIP FLOPS Department of IT Sarita Nahak Lect
Lecture 13 Topics Latches Flip Flops Algorithmic StateLecture 13 Topics Latches Flip Flops Algorithmic State
Sequential Logic and Flip Flops Sequential Logic CircuitsSequential Logic and Flip Flops Sequential Logic Circuits
Cruising with Flip Flops A MULTIDISCIPLINARY BUSINESS CASECruising with Flip Flops A MULTIDISCIPLINARY BUSINESS CASE
Building D Flip Flops Combinational Circuit Components SwitchesBuilding D Flip Flops Combinational Circuit Components Switches
COMPUTER ORGANIZATION Topics Combinational design Flip Flops CountersCOMPUTER ORGANIZATION Topics Combinational design Flip Flops Counters
Latches Flip Flops and Memory ECECS 252 FallLatches Flip Flops and Memory ECECS 252 Fall