CS 35101 Computer Architecture Spring 2006 Week 4

CS 35101 Computer Architecture Spring 2006 Week 4 Paul Durand (www. cs. kent. edu/~durand) Course url: www. cs. kent. edu/~durand/cs 35101. htm

Review: Signed Binary Representation -23 = -(23 - 1) = 1011 then add a 1 1010 complement all the bits 23 - 1 = 2’sc binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7

Review: MIPS Organization q Arithmetic instructions – to/from the register file q Load/store word and byte instructions – from/to memory Memory Processor 1… 1100 Register File src 1 addr src 2 addr dst addr write data src 1 data 32 5 5 5 32 registers ($zero - $ra) 32 read/write addr 32 src 2 32 data read data 32 32 bits write data Fetch 32 ALU Exec 230 words Decode 32 32 32 4 0 byte address (big Endian) 5 1 6 2 32 bits 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary)

Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) transfer store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 (I format) load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1

Head’s Up q This week’s material l MIPS Boolean operations; control flow operations; procedures - Reading assignment - PH 2. 5, 2. 6 q q Reminders l HW # 1 Due Friday, Feb 10 l Turn in via email with any assembler source code files included as attachments. Next week’s material l MIPS procedures cont’d. and addressing modes - Reading assignment - PH 2. 7, 2. 9, A. 5 and A. 6

Instructions for Making Decisions q Decision making instructions l l q alter the control flow i. e. , change the "next" instruction to be executed MIPS conditional branch instructions: bne $s 0, $s 1, Label $s 0 $s 1 beq $s 0, $s 1, Label $s 0=$s 1 q #go to Label if Example: if (i==j) h = i + j; Lab 1: bne $s 0, $s 1, Lab 1 add $s 3, $s 0, $s 1. . .

Assembling Branches q Instructions: bne $s 0, $s 1, Label $s 0 $s 1 beq $s 0, $s 1, Label $s 0=$s 1 q q #go to Label if op rs rt 5 16 17 ? ? 4 16 17 ? ? Machine Formats: 16 bit number I format How is the branch destination address specified?

Specifying Branch Destinations q Could specify the memory address - but that would require a 32 bit field q Could use a register (like lw and sw) and add to it the 16 -bit offset l which register? - Instruction Address Register (PC = program counter) - its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction PC bne $s 0, $s 1, Lab 1 add $s 3, $s 0, $s 1 Lab 1: . . . l limits the branch distance to -215 to +215 -1 instructions from the (instruction after the) branch instruction, but - most branches are local anyway (principle of locality)

Disassembling Branch Destinations q q The contents of the updated PC (PC+4) is added to the low order 16 bits of the branch instruction which is converted into a 32 bit value by l concatenated two low-order zeros to create an 18 bit number l sign-extending those 18 bits The result is written into the PC if the branch condition is true prior to the next Fetch cycle from the low order 16 bits of the branch instruction 16 offset sign-extend 00 32 32 Add PC 32 32 4 32 Add 32 32 branch dst address ?

Assembling Branches Example q Assembly code bne $s 0, $s 1, Lab 1 add $s 3, $s 0, $s 1. . . Lab 1: q q Machine Format of bne: op rs rt 5 16 17 16 bit offset I format 1 Remember l After the bne instruction is fetched, the PC is updated to address the add instruction (PC = PC + 4). l Two low-order zeros are concatenated to the offset number and that value sign-extended is added to the (updated) PC

MIPS Organization Processor Memory Register File src 1 addr src 2 addr dst addr write data 5 5 5 1… 1100 src 1 data 32 32 registers ($zero - $ra) read/write addr src 2 32 data 32 32 32 bits br offset 32 PC Fetch PC = PC+4 Exec 32 Add 4 32 Add read data 32 32 32 write data 32 Decode 230 words 32 32 ALU 32 32 4 0 5 1 6 2 32 bits byte address (big Endian) 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary)

Another Instruction for Changing Flow q MIPS also has an unconditional branch instruction or jump instruction: j q label Example: Lab 1: Lab 2: #go to label if (i!=j) h=i+j; else h=i-j; beq add j sub. . . $s 0, $s 1, Lab 1 $s 3, $s 0, $s 1 Lab 2 $s 3, $s 0, $s 1

Assembling Jumps q q Instruction: j label Machine Format: op 2 q #go to label 26 -bit address J format ? ? How is the jump destination address specified? l As an absolute address formed by - concatenating the upper 4 bits of the current PC (now PC+4) to the 26 -bit address and - concatenating 00 as the 2 low-order bits

Disassembling Jump Destinations q q The low order 26 bits of the jump instruction is converted into a 32 bit jump instruction destination address by l concatenated two low-order zeros to create an 28 bit (word) address and l concatenating the upper 4 bits of the current PC (now PC+4) to create a 32 bit instruction address that is place into the PC prior to the next Fetch cycle from the low order 26 bits of the jump instruction 26 00 32 32 PC 32

Assembling Branches and Jumps q Assemble the MIPS machine code (in decimal is fine) for the following code sequence. Assume that the address of the beq instruction is 0 x 00400020 (hex address) Lab 1: Lab 2: 0 x 00400020 0 x 00400024 0 x 00400028 0 x 0040002 c 0 x 00400030 beq add j sub. . . $s 0, $s 1, Lab 1 $s 3, $s 0, $s 1 Lab 2 $s 3, $s 0, $s 1 4 16 17 2 0 16 17 19 0 32 2 0000 0100 0. . . 0 0011 002 jmp dst = (0 x 0) 0 x 040003 002(002) = 0 x 00400030 0. . . 16 17 19 0 34

Compiling While Loops q Compile the assembly code for the C while loop where i is in $s 0, j is in $s 1, and k is in $s 2 while (i!=k) i=i+j; Loop: Exit: beq $s 0, $s 2, Exit add $s 0, $s 1 j Loop. . .

More Instructions for Making Decisions q We have beq, bne, but what about branch-if-lessthan? q New instruction: slt $t 0, $s 1 q Machine format: op rs 0 16 rt 17 # if $s 0 < $s 1 # then # $t 0 = 1 # else # $t 0 = 0 rd 8 funct 0 42 = 0 x 2 a 2

Other Branch Instructions q Can use slt, beq, bne, and the fixed value of 0 in register $zero to create all relative conditions l less than slt bne blt $s 1, $s 2, Label $t 0, $s 1, $s 2 $t 0, $zero, Label #$t 0 set to 1 if # $s 1 < $s 2 l less than or equal to ble $s 1, $s 2, Label l greater than bgt $s 1, $s 2, Label l great than or equal to bge $s 1, $s 2, Label q As pseudo instructions (get to practice with some of them in HW#2) - recognized (and expanded) by the assembler q The assembler needs a reserved register ($at) l there are policy of use conventions for registers

Another Instruction for Changing Flow q Most higher level languages have case or switch statements allowing the code to select one of many alternatives depending on a single value. q Instruction: jr q $t 1 #go to address in $t 1 Machine format: op rs 0 9 funct 0 0 0 8 = 0 x 08 2

Compiling a Case (Switch) Statement switch (k) { case 0: h=i+j; case 1: h=i+h; case 2: h=i-j; q break; /*k=0*/ break; /*k=1*/ break; /*k=2*/ $t 4 Assuming three sequential words in memory starting at the address in $t 4 have the addresses of the labels L 0, L 1, and L 2 and k is in $s 2 L 2: add add lw jr add j sub Exit: . . . L 0: L 1: $t 1, $t 0 $s 3, Exit $s 3, $s 2, $s 2 $t 1, $t 4 0($t 1) Memory L 0 L 1 L 2 $s 0, $s 1 #$t 1 = 2*k #$t 1 = 4*k #$t 1 = addr of JT[k] #$t 0 = JT[k] #jump based on $t 0 #k=0 so h=i+j $s 0, $s 3 #k=1 so h=i+h $s 0, $s 1 #k=2 so h=i-j

Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) transfer store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1 br on equal 4 beq $s 1, $s 2, L if ($s 1==$s 2) go to L br on not equal 5 bne $s 1, $s 2, L if ($s 1 !=$s 2) go to L (I format) Cond. Branch set on less than Uncond. Jump jump register 0 and 42 slt $s 1, $s 2, $s 3 2 j 2500 if ($s 2<$s 3) $s 1=1 else $s 1=0 go to 10000 0 and 8 jr $t 1 go to $t 1

Review: MIPS R 3000 ISA q Instruction Categories Registers R 0 - R 31 l Load/Store Computational Jump and Branch l Floating Point l l - coprocessor q l Memory Management PC HI l Special LO 3 Instruction Formats: all 32 bits wide 6 bits 5 bits rd OP rs rt OP 5 bits shamt 16 bit number 26 bit jump target 6 bits funct R format I format J format

Programming Styles q Procedures (subroutines) allow the programmer to structure programs making them l l q easier to understand debug and allowing code to be reused Procedures allow the programmer to concentrate on one portion of the code at a time l parameters act as barriers between the procedure and the rest of the program and data, allowing the procedure to be passed values (arguments) and to return values (results)

Six Steps in Execution of a Procedure q Main routine (caller) places parameters in a place where the procedure (callee) can access them l $a 0 - $a 3: four argument registers q Caller transfers control to the callee q Callee acquires the storage resources needed q Callee performs the desired task q Callee places the result value in a place where the caller can access it l q $v 0 - $v 1: two value registers for result values Callee returns control to the caller l $ra: one return address register to return to the point of origin

Instruction for Calling a Procedure q MIPS procedure call instruction: jal link Procedure. Address #jump and q Saves PC+4 in register $ra to link to the following instruction to set up the procedure return q Machine format: op 3 q J format 26 bit address ? ? Then can do procedure return with just jr $ra #return

Spilling Registers q What if the callee needs to use more registers than allocated to argument and return values? l it uses a stack – a last-in-first-out queue high addr q top of stack $sp One of the general registers, $sp, is used to address the stack (which “grows” from high address to low address) l add data onto the stack – push $sp = $sp – 4 data on stack at new $sp l low addr remove data from the stack – pop data from stack at $sp = $sp + 4

A Quick Aside q MIPS instruction for adding immediate values: addi $sp, 4 #$sp = $sp + 4 addi $sp, -4 #$sp = $sp - 4 q Another version of add in which one operand is a constant where the constant is kept inside the instruction itself q MIPS pseudoinstruction for multiplying: mul q $v 0, $a 0, $v 0 #$v 0 = $a 0 * $v 0 We will look at the machine representations for these instructions in the next lecture

Nested Procedures q Leaf procedures do not call other procedures. What happens to return addresses with nested procedures? int rt_1 (int i) { if (i == 0) return 0; else return rt_2(i-1); } caller: jal rt_1 next: . . . rt_1: to_2: rt_2: bne add jr addi jal jr. . . $a 0, $zero, to_2 $v 0, $zero $ra $a 0, -1 rt_2 $ra

Nested Procedures Outcome caller: jal rt_1 next: . . . rt_1: to_2: rt_2: q bne add jr addi jal jr $a 0, $zero, to_2 $v 0, $zero $ra $a 0, -1 rt_2 $ra . . . On the call to rt_1, the return address (next in the caller routine) gets stored in $ra. What happens to the value in $ra (when i != 0) when rt_1 makes a call to rt_2?

Saving the Return Address, Part 1 q Nested procedures (i passed in $a 0, return value in $v 0) high addr old TOS caller rt addr old $a 0 $sp low addr caller bk_2 rt addr $ra q rt_1: bne $a 0, $zero, to_2 add jr to_2: addi sw sw addi jal bk_2: lw lw addi jr $v 0, $ra $sp, $ra, $a 0, rt_2 $a 0, $ra, $sp, $ra $zero, $zero $sp, -8 4($sp) 0($sp) $a 0, -1 0($sp) 4($sp) $sp, 8 Save the return address (and arguments) on the stack

Saving the Return Address, Part 2 q Nested procedures (i passed in $a 0, return value in $v 0) high addr old TOS caller rt addr old $a 0 $sp low addr caller bk_2 rt addr $ra q rt_1: bne $a 0, $zero, to_2 add jr to_2: addi sw sw addi jal bk_2: lw lw addi jr $v 0, $ra $sp, $ra, $a 0, rt_2 $a 0, $ra, $sp, $ra $zero, $zero $sp, -8 4($sp) 0($sp) $a 0, -1 0($sp) 4($sp) $sp, 8 Save the return address (and arguments) on the stack

Compiling a Recursive Procedure q Calculating factorial: int fact (int n) { if (n < 1) return 1; else return (n * fact (n-1)); } q Recursive procedure (one that calls itself!) fact (0) = 1 fact (1) = 1 * 1 = 1 fact (2) = 2 * 1 = 2 fact (3) = 3 * 2 * 1 = 6 fact (4) = 4 * 3 * 2 * 1 = 24. . . q Assume n is passed in $a 0; result returned in $v 0

Compiling a Recursive Procedure fact: addi sw sw slt beq addi jr $sp, $ra, $a 0, $t 0, $v 0, $sp, $ra L 1: $a 0, -1 #n >=1, so decrement n fact #call fact with (n-1) is where fact returns $a 0, 0($sp) #restore argument n $ra, 4($sp) #restore return address $sp, 8 #adjust stack pointer $v 0, $a 0, $v 0 #$v 0 = n * fact(n-1) $ra #return to caller addi jal #this bk_f: lw lw addi mul jr $sp, -8 4($sp) 0($sp) $a 0, 1 $zero, L 1 $zero, 1 $sp, 8 #adjust stack pointer #save return address #save argument n #test for n < 1 #if n >=1, go to L 1 #else return 1 in $v 0 #adjust stack pointer #return to caller

A Look at the Stack for $a 0 = 2, Part 1 old TOS $sp caller rt addr $a 0 = 2 $sp q Stack state after execution of first encounter with the jal instruction (second call to fact routine with $a 0 now holding 1) l caller bk_f rt addr $ra 1 2 $a 0 $v 0 l saved return address to caller routine (i. e. , location in the main routine where first call to fact is made) on the stack saved original value of $a 0 on the stack

A Look at the Stack for $a 0 = 2, Part 2 old TOS caller rt addr $a 0 = 2 bk_f $a 0 = 1 $sp q Stack state after execution of second encounter with the jal instruction (third call to fact routine with $a 0 now holding 0) l bk_f $ra 0 1 $a 0 $v 0 l saved return address of instruction in caller routine (instruction after jal) on the stack saved previous value of $a 0 on the stack

A Look at the Stack for $a 0 = 2, Part 3 old TOS caller rt addr $a 0 = 2 bk_f $a 0 = 1 bk_f $a 0 = 0 q $sp bk_f $ra 0 $a 0 1 $v 0 Stack state after execution of first encounter with the first jr instruction ($v 0 initialized to 1) l stack pointer updated to point to third call to fact

A Look at the Stack for $a 0 = 2, Part 4 old TOS q caller rt addr $a 0 = 2 bk_f $a 0 = 1 bk_f $a 0 = 0 $sp bk_f $ra 0 1 $a 0 1 *1 1 $v 0 Stack state after execution of first encounter with the second jr instruction (return from fact routine after updating $v 0 to 1 * 1) l return address to caller routine (bk_f in fact routine) restored to $ra from the stack l previous value of $a 0 restored from the stack l stack pointer updated to point to second call to fact

A Look at the Stack for $a 0 = 2, Part 5 old TOS $sp caller rt addr $a 0 = 2 bk_f $a 0 = 1 bk_f $a 0 = 0 caller bk_f rt addr $sp q Stack state after execution of second encounter with the second jr instruction (return from fact routine after updating $v 0 to 1 * 2) l return address to caller routine (main routine) restored to $ra from the stack l original value of $a 0 restored from the stack pointer updated to point to first call to fact $ra l 1 2 $a 0 1 1 * * 1 1 * 2 $v 0

MIPS Register Convention Name Register Number $zero $v 0 - $v 1 $a 0 - $a 3 $t 0 - $t 7 $s 0 - $s 7 $t 8 - $t 9 $gp $sp $fp $ra 0 2 -3 4 -7 8 -15 16 -23 24 -25 28 29 30 31 Usage the constant 0 returned values arguments temporaries saved values temporaries global pointer stack pointer frame pointer return address Should preserve on call? n. a. no yes yes

Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) transfer store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1 br on equal 4 beq $s 1, $s 2, L if ($s 1==$s 2) go to L br on not equal 5 bne $s 1, $s 2, L if ($s 1 !=$s 2) go to L (I format) Cond. Branch set on less than Uncond. Jump 2 j 2500 if ($s 2<$s 3) $s 1=1 else $s 1=0 go to 10000 jump register 0 and 8 jr $t 1 go to $t 1 jump and link 3 jal 2500 go to 10000; $ra=PC+4 jump 0 and 42 slt $s 1, $s 2, $s 3