CS 35101 Computer Architecture Spring 2006 Week 5

CS 35101 Computer Architecture Spring 2006 Week 5 Paul Durand (www. cs. kent. edu/~durand) Course url: www. cs. kent. edu/~durand/cs 35101. htm

Head’s Up q This week’s material l MIPS procedures (cont’d), immediate instructions, and addressing modes - Reading assignment - PH 3. 6, A. 6 and 3. 8 l Translating a program - Reading assignment – PH 2. 10 – 2. 12 and A. 1 -A. 5 q q Reminders l HW 2 is due Monday, February 20 th (by midnight) l Midterm #1 – Thursday, February 23 rd Next week’s material

Review: MIPS Organization, so far Processor Memory Register File src 1 addr src 2 addr dst addr write data 5 5 5 1… 1100 src 1 data 32 32 registers ($zero - $ra) read/write addr src 2 32 data 32 32 32 bits br offset 32 PC Fetch PC = PC+4 Exec 32 Add 4 32 Add read data 32 32 32 write data 32 Decode 230 words 32 32 ALU 32 32 4 0 5 1 6 2 32 bits byte address (big Endian) 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary)

Cray was a legend in computers … said that he liked to hire inexperienced engineers right out of school, because they do not usually know what’s supposed to be impossible. The Soul of a New Machine, Kidder, pg. 77 CSE 331 W 05. 5 Irwin Fall 2001 PSU

Review: MIPS ISA, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data Transfer load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 (I format) load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1 Cond. Branch (I & R format) br on equal 4 beq $s 1, $s 2, L if ($s 1==$s 2) go to L br on not equal 5 bne $s 1, $s 2, L if ($s 1 !=$s 2) go to L Uncond. Jump (J & R format) jump CSE 331 W 05. 6 set on less than 0 and 42 slt $s 1, $s 2, $s 3 2 j 2500 if ($s 2<$s 3) $s 1=1 else $s 1=0 go to 10000 jump register 0 and 8 jr $t 1 go to $t 1 jump and link 3 jal 2500 go to 10000; $ra=PC+4 Irwin Fall 2001 PSU

Review: MIPS Organization, so far Processor Memory Register File src 1 addr src 2 addr dst addr write data 5 5 5 1… 1100 src 1 data 32 32 registers ($zero - $ra) read/write addr src 2 32 data 32 32 32 bits br offset 32 PC Fetch PC = PC+4 Exec 32 Add 4 32 Add read data 32 32 32 write data 32 Decode 230 words 32 32 ALU 32 32 4 0 5 1 32 bits byte address (big Endian) CSE 331 W 05. 7 6 2 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary) Irwin Fall 2001 PSU

Branching Far Away q What if the branch destination is further away than can be captured in 16 bits? q The assembler comes to the rescue – it inserts an unconditional jump to the branch target and inverts the condition beq $s 0, $s 1, L 1 bne j $s 0, $s 1, L 2 L 1 becomes L 2: CSE 331 W 05. 8 Irwin Fall 2001 PSU

Dealing with Constants q Small constants are used quite frequently (often 50% of operands) e. g. , q A = A + 5; B = B + 1; C = C - 18; Solutions? Why not? l put “typical constants” in memory and load them create hard-wired registers (like $zero) for constants like q Allow 1 for MIPS instructions like l addi slti andi ori q $sp, $t 0, $sp, $t 1, $t 0, 4 10 6 4 How do we make this work? CSE 331 W 05. 9 Irwin Fall 2001 PSU

Immediate Operands q MIPS immediate instructions: addi $sp, 4 slti $t 0, $s 2, 15 $s 2<15 q q op format: rs Machine rt #$sp = $sp + 4 #$t 0 = 1 if 16 bit immediate 8 29 29 4 10 18 8 15 I format The constant is kept inside the instruction itself! l l CSE 331 W 05. 10 I format – Immediate format Limits immediate values to the range +215– 1 to -215 Irwin Fall 2001 PSU

How About Larger Constants? q We'd also like to be able to load a 32 bit constant into a register q Must use two instructions, new "load upper immediate" instruction lui $t 0, 10101010 16 q 0 8 10101010 Then must get the lower order bits right, i. e. , ori $t 0, 1010101010101010 0000000000000000 1010101010101010 CSE 331 W 05. 12 10101010 Irwin Fall 2001 PSU

MIPS Addressing Modes q Register addressing – operand is in a register q Base (displacement) addressing – operand is at the memory location whose address is the sum of a register and a 16 -bit constant contained within the instruction q Immediate addressing – operand is a 16 -bit constant contained within the instruction q PC-relative addressing –instruction address is the sum of the PC and a 16 -bit constant contained within the instruction q Pseudo-direct addressing – instruction address is the 26 -bit constant contained within the instruction concatenated with the upper 4 bits of the PC CSE 331 W 05. 13 Irwin Fall 2001 PSU

Addressing Modes Illustrated 1. Register addressing op rs rt rd funct Register word operand 2. Base addressing op rs rt offset Memory word or byte operand base register 3. Immediate addressing op rs rt operand 4. PC-relative addressing op rs rt offset Memory branch destination instruction Program Counter (PC) 5. Pseudo-direct addressing op Memory jump address || jump destination instruction Program Counter (PC) CSE 331 W 05. 14 Irwin Fall 2001 PSU

Design Principles q Simplicity favors regularity l l q q Smaller is faster l limited instruction set l limited number of registers in register file l limited number of addressing modes Good design demands good compromises l q fixed size instructions – 32 -bits small number of instruction formats three instruction formats Make the common case fast l l CSE 331 W 05. 15 arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands Irwin Fall 2001 PSU

Review: MIPS ISA, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R & I format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 add immediate 8 addi $s 1, $s 2, 6 $s 1 = $s 2 + 6 or immediate 13 ori $s 1, $s 2, 6 $s 1 = $s 2 v 6 Data Transfer load word 35 lw $s 1, 24($s 2) $s 1 = Memory($s 2+24) store word 43 sw $s 1, 24($s 2) Memory($s 2+24) = $s 1 (I format) load byte 32 lb $s 1, 25($s 2) $s 1 = Memory($s 2+25) store byte 40 sb $s 1, 25($s 2) Memory($s 2+25) = $s 1 load upper imm 15 lui $s 1, 6 $s 1 = 6 * 216 br on equal 4 beq $s 1, $s 2, L if ($s 1==$s 2) go to L br on not equal 5 bne $s 1, $s 2, L if ($s 1 !=$s 2) go to L Cond. Branch (I & R format) Uncond. Jump (J & R format) CSE 331 W 05. 16 set on less than 0 and 42 slt $s 1, $s 2, $s 3 if ($s 2<$s 3) $s 1=1 else $s 1=0 if ($s 2<6) $s 1=1 else $s 1=0 set on less than immediate 10 slti $s 1, $s 2, 6 jump 2 j 2500 go to 10000 jump register 0 and 8 jr $t 1 go to $t 1 jump and link 3 jal 2500 go to 10000; $ra=PC+4 Irwin Fall 2001 PSU

The Code Translation Hierarchy C program compiler assembly code assembler object code library routines linker machine code executable loader memory

Compiler q Transforms the C program into an assembly language program q Advantages of high-level languages q l many fewer lines of code l easier to understand debug Today’s optimizing compilers can produce assembly code nearly as good as an assembly language programming expert and often better for large programs l l good – smaller code size, faster execution and even lower power consuming!

Assembler q Transforms symbolic assembler code into object (machine) code q Advantages of assembler l much easier than remembering instruction binary codes l can use labels for addresses – and let the assembler do the arithmetic l can use pseudo-instructions - e. g. , “move $t 0, $t 1” exists only in assembler (would be implemented using “add $t 0, $t 1, $zero”) q However, must remember that machine language is the underlying reality l q e. g. , destination is no longer specified first And, when considering performance, you should count real instructions executed, not code size

Other Tasks of the Assembler q Determines binary addresses corresponding to all labels l keeps track of labels used in branches and data transfer instructions in a symbol table - pairs of symbols and addresses q Converts pseudo-instructions to legal assembly code l register $at is reserved for the assembler to do this q Converts branches to far away locations into a branch followed by a jump q Converts instructions with large immediates into a load upper immediate followed by an or immediate q Converts numbers specified in decimal and hexidecimal into their binary equivalents q Converts characters into their ASCII equivalents

Typical Object File Pieces q Object file header: size and position of following pieces q Text module: assembled object (machine) code q Data module: data accompanying the code l static data - allocated throughout the program l dynamic data - grows and shrinks as needed by the program q Relocation information: identifies instructions (data) that use (are located at) absolute addresses – those that are not relative to a register (e. g. , jump destination addr) – when the code and data is loaded into memory q Symbol table: remaining undefined labels (e. g. , external references) q Debugging information

MIPS (spim) Memory Allocation Memory Mem Map I/O $sp Kernel Code & Data fffffffc 8000 0080 7 f f e f f fc Stack 230 words Dynamic data $gp Static data 1000 8000 ( 1004 0000) 1000 0000 Your Code PC Reserved 0040 0000

Linker q Takes all of the independently assembled code segments and “stitches” (links) them together l q Much faster to patch code and recompile and reassemble that patched routine, than it is to recompile and reassemble the entire program Decides on memory allocation pattern for the code and data modules of each segment l remember, segments were assembled in isolation so each assumes its code’s starting location is 0 x 0040 0000 and its static data starting location is 0 x 1000 0000 q Absolute addresses must be relocated to reflect the new starting location of each code and data module q Uses the symbol table information to resolve all remaining undefined labels l branches, jumps, and data addresses to external segments

Loader q Loads (copies) the executable code now stored on disk into memory at the starting address specified by the operating system q Initializes the machine registers and sets the stack pointer to the first free location (0 x 7 ffe fffc) q Copies the parameters (if any) to the main routine onto the stack q Jumps to a start-up routine (at PC addr 0 x 0040 0000 on xspim) that copies the parameters into the argument registers and then calls the main routine of the program with a jal main