CMPUT 229 Fall 2003 Topic E Building a

CMPUT 229 - Fall 2003 Topic. E: Building a Data Path and a Control Path for a Microprocessor José Nelson Amaral CMPUT 329 - Computer Organization and Architecture II 1

Representing Instructions: R-Type Instructions add $8, $17, $18 This instruction has 3 operands. The data that is operates on is stored in registers. It adds the content of registers $17 and $18 and stores the result in register $8. Its meaning can be summarized as follows: $8 $17 + $18 Op. Code 0 rs 17 rt 18 31 26 000000 25 21 10001 20 16 10010 Destination shiftamt 8 0 15 11 01000 10 6 00000 function 32 5 0 100000 R-Type Instruction Format CMPUT 329 - Computer Organization and Architecture II 2

Representing Instructions: Memory Instructions lw $7, 68($9) Read the memory location addressed by the value in register $9 plus 68 and store the value in register $7 Its meaning can be summarized as follows: $7 Memory[$9 + 68] Op. Code 35 rs 9 rt 7 address 68 31 26 100001 25 21 01001 20 16 00111 15 0 00000100 I-Type Instruction Format CMPUT 329 - Computer Organization and Architecture II 3

Representing Instructions: Memory Instructions sw $13, 56($17) Write the value currently in register $13 in the memory location addressed by the value in register $17 plus 56 Its meaning can be summarized as follows: Memory[$17 + 56] $13 Op. Code 43 rs 17 rt 13 address 56 31 26 101011 25 21 10001 20 16 01101 15 0 00000111000 I-Type Instruction Format CMPUT 329 - Computer Organization and Architecture II 4

Representing Instructions: Branch Instructions bne $1, $2, 100 Add 4 to the PC. If the value in register $1 is not equal the value in register $2, then add 100 to the PC before fetching the next instruction. Its meaning can be summarized as follows: PC + 4 if($1 $2) PC + 100 Op. Code 5 rs 1 rt 2 address 100 31 26 000101 25 21 00001 20 16 00010 15 0 000001100100 I-Type Instruction Format CMPUT 329 - Computer Organization and Architecture II 5

Building a Datapath: Instruction Memory Write Read address PC Memory Adder Sum Instruction Program Counter Instruction Memory CMPUT 329 - Computer Organization and Architecture II Adder 6

Building a Datapath PC Incrementer Adder Sum Write PC 4 Read address Memory Instruction CMPUT 329 - Computer Organization and Architecture II 7

Building a Data Path Register File and ALU Reg. Write 5 5 5 32 Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 32 32 Data Register File CMPUT 329 - Computer Organization and Architecture II Zero ALU result ALU operation ALU 8

A Two Read Port File with n Registers Reg. Write Read Register 1 C Reg. 0 D C Reg. 1 D Write Register 5 -to-32 decoder C D 32 • • • C Reg. n-2 D Write Data Read Register 2 M u x CReg. n-1 D CMPUT 329 - Computer Organization and Architecture II M u x 32 9

Read Register 1 5 R 0_0 R 1_0 R 31_0 R 0_1 R 1_1 R 31_1 R 0_31 R 1_31 • • • M u x 1 R 31_31 R 0 R 1 R 31 Read Register 1 Reg. 0 Reg. 1 M u x 32 CMPUT 329 - Computer Organization and Architecture II 10

Building a Data Path R-Type Instruction Reg. Write I(25 -21) Instruction I(20 -16) I(15 -11) 32 Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 32 32 Zero ALU result ALU operation add $8, $17, $18 Op. Code 0 rs 17 rt 18 31 26 000000 25 21 10001 20 16 10010 Destination shiftamt 8 0 15 11 01000 CMPUT 329 - Computer Organization and Architecture II 10 6 00000 function 32 5 0 100000 11

Building a Data Path Load/Store Instructions Mem. Read Mem. Write Read address Data Memory Write address Mem. Data Write data Data Memory Unit 16 Sign ext. 32 Sign-extension Unit CMPUT 329 - Computer Organization and Architecture II 12

Building a Data. Path Load/Store Instructions Reg. Write I(25 -21) Instruction I(20 -16) 32 Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 Sign ext. 32 Mem. Read Zero ALU result ALU operation Read address Data Memory Write address Mem. Data Write data 32 lw $7, 68($9) Op. Code 35 31 26 100001 rs rt 9 7 25 21 20 16 01001 CMPUT 00111 329 - Computer Organization and Architecture II address 68 15 0 00000100 13

Building a Data. Path Load/Store Instructions Mem. Write I(25 -21) Instruction I(20 -16) Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 16 Op. Code 43 31 26 101011 Sign ext. Zero ALU result ALU operation Read address Data Memory Write address Mem. Data Write data 32 sw $13, 56($17) rs rt 17 13 25 21 20 16 10001 CMPUT 01101 329 - Computer Organization and Architecture II address 56 15 0 00000111000 14

Combining Memory and Register Instr. Datapaths Reg. Write Instruction 32 Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers ALUSrc Mem. Read Zero ALU result ALU 0 M u 1 x ALU operation 16 Sign ext. Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data 0 M u 1 x 32 sw $13, 56($17) Op. Code 43 rs 17 add $8, $17, $18 Op. Code 0 rs 17 rt 13 address 56 rt Destination shiftamt CMPUT 329 18 - Computer 8 0 Organization and Architecture II function 32 15

Building a Data. Path Branch Instructions Adder PC + 4 Sum Shift left 2 I(25 -21) Instruction I(20 -16) Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 bne $1, $2, 100 Op. Code 5 31 26 000101 Sign ext. 32 32 Zero Branch Target To branch control logic ALU operation 32 rs rt 1 2 25 21 20 16 00001 CMPUT 00010 329 - Computer Organization and Architecture II address 100 15 0 000001100100 16

Building a Data. Path Branch Instructions Adder PC + 4 Sum Shift left 2 Reg. Write I(25 -21) Instruction I(20 -16) Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 bne $1, $2, 100 Op. Code 5 31 26 000101 Sign ext. 32 32 Zero Branch Target To branch control logic ALU operation 32 rs rt 1 2 25 21 20 16 00001 CMPUT 00010 329 - Computer Organization and Architecture II address 100 15 0 000001100100 17

0 Adder Sum Write PC Sum 4 Shift left 2 M u 1 x PCSrc Read address Memory Instruction Reg. Write Instruction 32 Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Zero ALU result ALU Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II 18

Destination Register for Load and R-Type Instr. lw $7, 68($9) Op. Code 35 31 26 rs 9 25 21 rt 7 20 16 address 68 15 0 add $8, $17, $18 Op. Code 0 31 26 rs 17 25 21 rt 18 20 16 Destination shiftamt 8 0 15 11 10 6 function 32 5 0 The Destination register of a load is specified in I 20 -I 16, but for an R-Type instruction the destination is specified by the bits I 15 -I 11. Therefore we need a multiplex in the data path of the write register. CMPUT 329 - Computer Organization and Architecture II 19

0 Adder Sum Write PC Sum 4 Shift left 2 M u 1 x PCSrc Read address Memory Instruction Reg. Write Reg. Dst I(25 -21) I(20 -16) 0 M I(15 -11) u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 I(15 -0) 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 20

Four Steps of an R-type Instruction 1. Fetch Instruction from instruction memory, and increment PC. 2. Read two registers (I 25 -I 21) and (I 20 -I 16) from the register file. 3. Use bits I 5 -I 0 from the instruction code to determine the function that the ALU performs on the data read from the register file. 4. Write the ALU result to the destination register (I 15 -I 11). CMPUT 329 - Computer Organization and Architecture II 21

0 Adder Sum Write PC Sum 4 Shift left 2 R-Type Instruction First Step: Instruction Fetch Memory Instruction Reg. Write Reg. Dst I(20 -16) 0 M I(15 -11) PCSrc Read address I(25 -21) u 1 x M u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 22

0 Adder Sum Write PC Sum 4 Shift left 2 R-Type Instruction Second Step: Read Source Registers Memory Instruction Reg. Write Reg. Dst I(20 -16) 0 M I(15 -11) PCSrc Read address I(25 -21) u 1 x M u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 23

0 Adder Sum Write PC Sum 4 Shift left 2 R-Type Instruction Third Step: ALU Operates on Registers Memory Instruction Reg. Write Reg. Dst I(20 -16) 0 M I(15 -11) PCSrc Read address I(25 -21) u 1 x M u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 24

0 Adder Sum Write PC Sum 4 Shift left 2 R-Type Instruction Final Step: Write the Result Memory Instruction Reg. Write Reg. Dst I(20 -16) 0 M I(15 -11) PCSrc Read address I(25 -21) u 1 x M u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 25

Four Steps for a load Instruction 1. Fetch Instruction from instruction memory, and increment PC. 2. Read one register (I 25 -I 21) from the register file. 3. The ALU computes the sum of the value read from the register file and the sign-extended lower 16 bits of the instruction (offset). 4. Use the result of the ALU as an address to the data memory. 5. Write the data from the memory unit to the destination register (I 20 -I 16). CMPUT 329 - Computer Organization and Architecture II 26

0 Adder Sum Write PC Sum 4 Shift left 2 Data. Path for a Load Instruction Reg. Write Reg. Dst I(25 -21) I(20 -16) 0 M I(15 -11) PCSrc Read address Memory u 1 x M u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 27

Four Steps for a branch-onequal Instruction 1. Fetch Instruction from instruction memory, and increment PC. 2. Read two registers (I 25 -I 21) and (I 20 -I 16) from the register file. 3. The ALU subtracts the data values read from the register. Add the value PC + 4 to the sign-extended lower 16 bits of the instruction (offset) --- the result is the branch target. 4. Use the zero result from the ALU to decide which adder result to store in the PC (either the branch target or PC+4). CMPUT 329 - Computer Organization and Architecture II 28

0 Adder Sum Write PC Sum 4 Shift left 2 PCSrc Read address Memory M u 1 x Data. Path for a Branch Instruction Branch Reg. Write Reg. Dst I(25 -21) I(20 -16) 0 M I(15 -11) u 1 x Read register 1 Read 32 data 1 Read register 2 Write Read 32 register data 2 Write data Registers 32 16 I(5 -0) Sign ext. 32 ALUSrc 0 M u 1 x Mem. Read Mem. Write Memto. Reg Read address Data Memory Write address Mem. Data Write data Zero ALU result ALU 0 M u 1 x ALU control CMPUT 329 - Computer Organization and Architecture II ALUOp 29