Chapter 13 IO Systems Pgs 555 586 CSCI

Chapter 13 – I/O Systems (Pgs 555 -586 ) CSCI 3431: OPERATING SYSTEMS

Devices Two conflicting properties A. Growing uniformity in interfaces (both h/w and s/w): e. g. , USB, TWAIN B. Growing disparity in device characteristics: e. g. , haptic devices, speakers, monitors, plotters, network adapters

Device Categories Various ways to categorise devices Input: computer receives data Output: computer sends data Storage: data storage Transmission : interdevice communication Human Interface: HCI Sensory: monitoring of conditions Feedback: input in response to output . . . etc. . .

Busses A data communication path (wires) with a predefined protocol A port is a connection to the bus A controller, which is often has a separate processor and memory, may operate a port, bus, device, or some combination of them The bus speed ("timing") is often different to the CPU clock speed, and is affected by the connection characteristics and bus length PCIe (16 GB) – Peripheral Component Interconnect, Express SCSI – Small Computer System Interface USB – Universal Serial Bus

A Typical PC Bus Structure

Controller IO Controllers have registers To send data to these registers, there are two communication methods 1. memory-mapped IO: registers mapped into the CPU's address space, i. e. , use same address bus to access memory and IO devices 2. port-mapped IO: uses special CPU instructions (e. g. , outb, outw), special IO lines, and perhaps an IO bus Intel PCs use both methods

Ports Typically have 4 registers 1. Data-In: to receive data, via the port 2. Data-Out: to send data out, via the port 3. Status: bits that describe the port's status 4. Control: bits to initiate IO, change mode, and perform operations

Port IO and Polling Host: 1. 2. 3. 4. Read (status) busy bit until clear – "Polling" Write byte into (data-out) register Set (command) write bit Set (command) command-ready bit Controller: 5. 6. 7. 8. 9. Set (status) busy bit Interpret the (command) register Do the command – transfer outgoing data Clear (status) command-ready bit, error bit Clear busy bit

Interrupts Avoid need to poll devices Uses special lines to the CPU, 2 Lines: 1. 2. Maskable (for general IO) Unmaskable for critical interrupts Address bus usually contains offset into interrupt vector for interrupt handler Interrupt lines checked after every CPU instruction cycle Handlers are chained together if there are more handlers than vector slots (about 256) Interrupts are typically given a priority level in case they are interrupted themselves (to see which one is executed)

Direct Memory Access (DMA) Using CPU to move bytes from memory to IO port/controller is a waste of CPU time Special controller (DMA Controller) serves as a CPU proxy and does the transfer to free-up the CPU cannot access memory while DMA controller has control of memory bus (but can use cache)

DMA Transfer

Device Drivers OS Kernel has an IO subsystem Device drivers abstract the details of the device so IO subsystem can have a common interface to devices Permit H/W manufacturers more freedom Extra layer between device controller and OS specific so a device can work on many different platforms ioctl() is generic and permits applications to interface with the device driver directly

Kernel IO Structure

IO Device Properties Transfer Mode: character | block Access Method: sequential | random Transfer Schedule: a/synchronous Sharing: dedicated | shared Device Speed: latency, seek time, transfer rate, inter-op delays, refresh cycle Transfer Direction: read | write | read/write

Clocks and Timers Systems have a built-in timer "clock" as a device – Variable Interval Timer Can be programmed to provide an interrupt at a set time Used by scheduler but also available for user processes Based on counting clock cycles Various hardware implementation methods

An IO request (blocking read) Application calls read() OS validates request, checks buffers (returns buffered data if possible) 3. Move process it device IO queue, IO scheduled for sending to device driver 4. Device driver requests space for result 5. Device driver has device perform data transfer 6. DMA controller (0 r device) sends interrupt to say transfer of data complete 7. Interrupt handler sorts out what was happening and signals device driver that transfer is done 8. Device driver does post transfer actions and signals OS 9. OS unblocks process and runs scheduler 1. 2.

IO Requests

Performance Lots of context switches to stress CPU and hardware caches Considerable bus use for data transfer and buffering Lots of interrupts, sometimes 3 or 4 per IO request Fully exposes any weakness in the OS One of the primary focuses of OS design

To Improve Performance Reduce number of context switches Reduce data transfers and copies Reduce number of interrupts – larger transfers and more buffering Increase concurrency – let controllers do more work Move work into the hardware and controller

A New IO Algorithm

Operating Systems 1. 2. 3. 4. 5. Interrupt Mechanism Processes/Threads + Scheduler Interprocess Communication Memory Management IO Interfaces Performance Reliability

To Do: Finish Assignment 3 (Due last day of classes) Read Chapters 1 to 13 (The assigned course readings; all lectures) Study for the Final Exam