Building Silicon IP and SubSystems for Automotive Infotainment
Building Silicon IP and Sub-Systems for Automotive Infotainment and ADAS Applications Charles Qi System Solutions Architect Embedded Tech. Con 6/10/2015
Automotive industry: the first and the future Ford Model T in 1915 The First Massively Produced Car Electronic components: Spark plug, headlight, and horn Current supply: Flywheel-mounted magneto 2 © 2015 Cadence Design Systems, Inc. All rights reserved. . Poster at 2015 SAE Congress Future Self-driving Vehicle
Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 3 © 2015 Cadence Design Systems, Inc. All rights reserved. .
New applications drive increased complexity • Balanced growth in overall automotive semiconductor • Significant growth for ADAS and infotainment applications Image courtesy of: BIMMERPOST. com F 30 General Vehicle Electronics High-end cars today have more than 100 ECUs! 4 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Increased demand on computation power Over 1000 GOPS required for vision processing Increased Application Complexity Increased Algorithm Complexity Generalization HAAR SVM HOG SIFT Canny Harris SURF Lo. G/Do. G Time of Deployment 5 © 2015 Cadence Design Systems, Inc. All rights reserved. . CNN
Increased demand on network/memory bandwidth • Resolution • Frame rate • # of stream/camera • Intermediate data 6 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Disruption to automotive E/E supply chain Opportunity for silicon and IP vendors to participate at system level EDA/IP Vendors 7 Tier 2 Semi Tier 1 System © 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other © 2015 Cadence Design Systems, Inc. All rights reserved. . trademarks are the property of their respective owners and are not affiliated with Cadence. OEM
Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 8 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Diversity and complexity of ADAS applications Demands high-performance and flexible compute platform Vision Radar Vision Radar Audio Vision Audio Radar Vision Figure courtesy of: TI 9 Vision Audio/Sound Radar Rear Object Detection Parking Assist/Auto Park Voice Recognition Cabin Noise Reduction Emergency Recognition Front Collision Avoidance Braking Adaptive Cruise Control 360 degree Hazard Awareness © 2015 Cadence Design Systems, Inc. All rights reserved. . Rear Collision Detection Vision Rear View Camera Vision Enhancement Auto dimming headlights Blind Spot Detection 360 View Parking Assist Sign Recognition Traffic Signal Detection Lane Detection Rain/Fog Detection Pedestrian Avoidance Eye Focus Detection Driver Monitoring Sign Recognition Vehicle Detection
Xtensa offer scalable performance, flexibility Architecture with fully automated HW and SW tools generation Custom Instructions (optional) Set configuration options (optional) Choose processor template Xtensa Processor Generator Outputs Hardware EDA scripts RTL System Modeling / Design Software Tools Instruction Set Simulator (ISS) Xplorer IDE Graphical User Interface to all tools Fast Function Simulator (Turbo. Xim) Synthesis Block Place & Route XTSC System Modeling Verification Chip Integration / Co-verification To Fab / FPGA 10 Pin-Level Co -simulation XTMP Cbased System Modeling GNU Software Toolkit (Assembler, Linker, Debugger, Profiler) Xtensa C/C++ (XCC) Compiler C Software Libraries Operating Systems System Development © 2015 Cadence Design Systems, Inc. All rights reserved. . Software Development Application Source C/C++ Compile Executable Profile Using ISS Optimize using Configuration configuration - or Develop options. Custom Instructions
Customization of various DSP cores Function-specific Optimization Multiple products, same base architecture and development tools Xtensa Foundation Customize Designer-defined extensions Configure Click-box options Hi. Fi 4 Hi. Fi 3 Fusion Hi. Fi EP Hi. Fi Mini Hi. Fi 2 Conn. X D 2, BBE 16 BBE 32/64 EP BSP 3 SSP 16 Turbo 16 MS IVP-EP IVP 32 Single or Multicore Subsystem Base ISA Optimized DSPs and Controllers Audio Communications Baseband Imaging and Vision Customize Designer-defined extensions • • Instruction set Register/state IO queues Memory Configure Click-box options LX 6 Xtensa 11 Applications 11 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Vision DSP Ideal for ADAS Computation Demands Scalable high-performance at low power • High Performance AXI 192 x 8 b vector 96 x 16 b vector 32 x 32 b vector IVP-EP Vision Core AXI Micro DMA I RAM 4 x 32 b scalar 96 x 16 b vector 32 x 32 b vector IVP-EP Vision Core Data RAM I Cache Micro DMA I RAM 4 x 32 b scalar I Cache 192 x 8 b vector Data RAM – VLIW and 64 way SIMD – Designed for Multiprocessor – 24 x power-normalized performance of standard CPU – Expandable with TIE • Low Power – 70 mw to <300 m. W – 1/6 the power of standard CPU • Small Size – Optimized for 40 nm, 28 nm, and 14 -16 nm FF technologies – ¼ the size of a GPU with better power/performance 12 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Rich, vision DSP-optimized software Vision kernel library, standard API, reference applications Open. CV and Open. VX Library • 800 library functions optimized for IVP-EP • Planned Open. VX support Imaging/Vision Kernels • • High-performance Sobel, median, Gaussian filters SIFT, SURF, Harris Corner: detection algorithm HOG, HAAR: object detection and classification LK: optical flow Imaging/Vision Application Support • • • HDR, video WDR Image stabilization Face/people detection Face recognition More unannounced This roadmap is provided for informational purposes only and does not represent a commitment to deliver any of the features or functionality discussed in the materials. 13 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 14 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Network technology existed in E/E architecture Mix of low data rate control or high-cost/proprietary solutions • Low data rate control Technology Data Rate IP Ownership Media Topology Usage LIN 40 kbps LIN Consortium Single wire P 2 P Body electronics CAN 1 Mbps ISO-11898 Bosch UTP Shared Power train (Engine, transmission, ABS) CAN-FD 2. 5 Mbps Bosch UTP Shared Power train (Engine, transmission, ABS) Flex. Ray 10 Mbps ISO-17458 Flex. Ray Consortium UTP Shared High-perf power train, (Safety, drive-by-wire, active suspension, ACC) • High cost/proprietary Technology Data Rate IP Ownership Media Topology Usage MOST 150 Mbps SMSC POF Ring infotainment FPDLink LVDS 655 Mbps – 3 Gbps TI/National Shield coax P 2 P Camera/display 15 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Ethernet streamlines automotive E/E architecture From low BW, proprietary, control-centric to high BW, standard-based data network Standardization – Time synchronization – Qo. S – Redundancy – VLAN isolation – Power efficiency – PHY Bandwidth scalability – 100 Mbps – 1 Gbps – Scales up to 400 Gbps Large eco-system – Wide deployment – Long-lasting part supply Low cost – Design to drive UTP – Volume drives down ASP 16 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Automotive application endorsed by IEEE standards Change best-effort network to reliable network for automotive AVB: time sync, reserve and guarantee BW 1588 802. 1 AS 2011 1588: timing and synchronization for time sync network. 802. 1 AS is Ethernet bridged network profile of 1588 1722 a Layer 2 transport protocol for time-sensitive streams, also known as AVBTP 802. 1 Qav Forwarding and queuing enhancements for time-sensitive streams, traffic class, priority and credit-based shaping 802. 1 Qat Stream reservation protocol (SRP) 802. 1 BA AVB network system and AVB profile TSN: reduce and guarantee latency, redundancy 802. 1 ASREV AS Improvements: one step time stamping, redundant grand master clock and fast failover, redundant sync message path 802. 1 Qbu Packet preemption 802. 1 Qbv Time-aware traffic scheduling 802. 1 Qcc SRP improvements: reduce size/frequency of SRP messaging, interoperation with IGMP 802. 1 CB Frame replication and elimination for reliability Automotive PHY: low-cost, onepair UTP cable, better EMI 17 802. 3 bw 100 Mb/s PHY over single balanced twisted pair cable, also known as 100 BASE-T 1 15 m, 1 pair UTP, full-duplex operation, PAM 3 encoding 802. 3 bp 1 Gb/s PHY over single balanced twisted pair cable, also known as 1000 BASE-T 1 15 m, 1 pair UTP, full-duplex operation, PAM 3 encoding, RS FEC © 2015 Cadence Design Systems, Inc. All rights reserved. .
Cadence Automotive Ethernet MAC IP Address in-car network bottleneck with dedicated HW features • Scalable Performance Packet Buffer Tx AHB/AXI APB AHB/AXI master APB DMA Config Reg AVB Queue MAC filter L 3/L 4 FCS Pause MIB Stats 1588 TSU Rx – 100 Mbps, 1 Gbps data rate – Advanced DMA • IEEE 802. 1 Qav Qo. S MDIO – Multiple HW priority queues – Credit-based traffic shaping • IEEE 1588/802. 1 AS Time Sync – PTP frame detection – 1 -step or 2 -step clock adjustment – High-resolution HW time-stamping • Power Management – Energy Efficient Ethernet state control – Wo. LAN packet detection • Safety and Reliability PCS RGMII 18 GMII(MII) TBI © 2015 Cadence Design Systems, Inc. All rights reserved. . – FCS generation and checking – Overrun/underrun error detection – Maskable interrupt on error conditions
Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 19 © 2015 Cadence Design Systems, Inc. All rights reserved. .
LPDDR 4 is ideal technology for automotive Solving memory BW demand with optimized cost, power, and reliability High Performance – 3200 Mbps rate – > 20 GBps (x 32) – 2 X of LPDDR 3 LPDDR 4: Optimized Memory Solution Better SI, Lower EMI – Rich training – DBI – VSS termination 20 Figure courtesy of: Samsung JEDEC Presentation Low cost, long-lasting supply guaranteed by mobile adoption © 2015 Cadence Design Systems, Inc. All rights reserved. . Low Power – Low-swing I/O – DFS support – DBI – 40% < DDR 4 Higher Reliability – 1 st with PPR – Extended op. range – Temp compensation
Cadence DDR IP Solution • DDR Controller IP DDR PHY IP Memory VIP Data LPDDR 1 LPDDR 2 LP 2 NVM LPDDR 3 LPDDR 4 IO Data CMD Data – High performance – Multi-queue, request re-ordering, page policy – Advanced reliability features DDR 1 DDR 2 DDR 3 DDR 4 Wide-IO Combos Data DFI Port Arbitration Command Queue Port 0 Port n DDR Controller IP 16 FF+ DDR IP TC – CRC, ECC, inline ECC, BIST – Low power features – DFS, DFI LPI, power down control per CS, DBI • DDR PHY IP – Scalable DDR PHY architecture – targeting 4266 Mb/s – PHY low power states – Light sleep/ Deep sleep/Retention – Silicon proven in many generations – 28 nm, 14 -16 nm advance nodes • Comprehensive Solution – LPDDR 4/3, DDR 4/3 up to 3200 Mb/s – Verified with industry-leading memory models – Silicon validated full DDR sub-system 21 Cadence Confidential. © 2015 Cadence Design Systems, Inc. All rights reserved. .
Cadence Camera Interface IP Solution MIPI CSI-2 controller and D-PHY total solution • Standard Compliant – MIPI CSI-2 v 1. 1 compliant controller – MIPI D-PHY v 1. 1 compliant PHY • High Performance – – High resolution pixel interface Any lane configuration, x 1~ x 4 HS 1. 5 Gbps data transfer per lane Virtual channel support • Low Power – ULPS and Contention Detection mode – Auto termination control for HS and LP modes • Reliability – Integrated PRBS, CRPAT, CJTPAT • Integrated Solution – – 22 © 2015 Cadence Design Systems, Inc. All rights reserved. . Pre-integrated and verified Reference VIP integration Reference software drivers FPGA demo platforms
Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 23 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Sub-system Solution Reduces Customer TTM pre-validated HW/SW reference sub-system ensures integration quality DDR LPDDR Wide. IO HBM, HMC SD/e. MMC UFS Memory & Storage IP NAND Flash ONFi, TGL Interface IP AFE Ethernet CPU/GPU ARM/x 86 DSP PCIe Audio/Voice USB Image/video MIPI AMS/Analog IP ADC/DAC Custom Logic Memory M-PCIe SSIC Sensors PVT SDIO Processing IP LDO POR PLL DLL Baseband HDMI, MHL DP/e. DP Peripheral IP VIP support for all major protocols and memory models Systems Peripherals Speed-up customer HW/SW integration, ensure product quality and reliability 24 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Example automotive AV sub-systems Representative infotainment and ADAS system topology Ethernet AVB domain Video EP auto. E PHY Tensilica Vision Auto. E MAC DPHY CSI-2 PPI MII UTP Centralized ECU for Infotainment or ADAS Video EP auto. E PHY Tensilica Vision Auto. E MAC DPHY CSI-2 PPI UTP MII AVB switch DDR Audio EP MII Auto. E MAC MII UTP e. MMC Audio EP 25 I 2 S Sound. Wire Audio DAC AMP Apps PCIe PHY USB PHY DSI DPHY auto. E PHY Tensilica Hi. Fi Auto. E MAC I 2 S Sound. Wire Audi o DAC AMP Auto. E MAC MII PCIe auto. E PHY Tensilica Hi. Fi © 2015 Cadence Design Systems, Inc. All rights reserved. . UTP
Putting the sub-systems into prototyping demos Effective demonstration of integrated sub-systems for automotive Analog audio Audio Subsystem So. C Platform Auto. E MAC BRPHY Sound Wire Tensilica Hi. Fi Auto. E AVB switch D-PHY Video Subsystem Auto. E MAC MIPI CSI Tensilica Vision Time-sync audio: 2014 IEEE-SA 26 BRPHY Automotive Ethernet Face detection: 2015 MWC © 2015 Cadence Design Systems, Inc. All rights reserved. . Pedestrian detection: 2015 EVS
Unified sub-system development flow Validating every phase of the IP integration Simulation and VSP SW/HW Co-development RIPE 2 Prototyping Single IP/Small Sub-system Protium™ So. C Validation Small/medium So. C 27 © 2015 Cadence Design Systems, Inc. All rights reserved. . RIPE 3 Prototyping Large Sub-system Palladium® Emulation Large So. C/SW Integration
Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 28 © 2015 Cadence Design Systems, Inc. All rights reserved. .
Hard IP qualification for AEC-Q 100 Increased circuit design and silicon testing effort • Hard IP in GDS no long sufficient • Production gated by AEC-Q 100 qualification Test Item Stringent Test Requirements Large Sample Size ELFR • • Grade 0: 48 hours at 150°C or 24 hours at 175°C Grade 1: 48 hours at 125°C or 24 hours at 150°C Grade 2: 48 hours at 105°C or 24 hours at 125°C Grade 3: 48 hours at 85°C or 24 hours at 105°C 3 lots, 800 parts per lot HTOL • • Grade 0: +150ºC Ta for 1000 hours Grade 1: +125ºC Ta for 1000 hours Grade 2: +105ºC Ta for 1000 hours Grade 3: +85ºC Ta for 1000 hours 3 lots, 77 parts per lot ESD (HBM) • Classification 2 or better • Conducted at 500 V, 1000 V and 2000 V • Some product might require up to 7000 V (# of 250 V voltage steps) x 3 ESD (CDM) • Classification C 4 B or better • 750 V corner pins, 500 V for all other pins (# of 250 V voltage steps) x 3 Latch-up • Negative/positive current and over voltage testing 6 parts from 1 lot Characterization • CHAR plan should cover PPM target, corner lots, sample sizes, etc. No hard-specific requirements provided Multiple parts from corner lots # driven by test accuracy 29 © 2015 Cadence Design Systems, Inc. All rights reserved. .
IP development for functional safety Enhancing design process, tool qualification, and HW features • ISO 26262 provides requirements at system level • Requirements propagate down to IP developments Process Documentation 30 • Functional safety training • Designated functional safety manager, separate design/validation roles • Traceable requirements and specifications • ISO 9001 quality control • Functional requirements and architecture/design specifications • Safety manual / user’s guide • Verification reports • FMEA / FMEDA Tools and Software • Toolchain validation and compliance • C library validation and compliance • Middleware DSP library validation Design Features • Data protection and error detection • Memory protection and task isolation • Low-latency deterministic operation © 2015 Cadence Design Systems, Inc. All rights reserved. .
Conclusion Automotive market presents significant opportunity and challenge 31 © 2015 Cadence Design Systems, Inc. All rights reserved. . Cadence is the trusted partner to provide you the right IP solutions
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Palladium, and Xtensa are registered trademarks and Protium is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
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