Agenda Day Two DAY 2 Unit 7 1

Agenda: Day Two DAY 2 Unit 7 -1 Topic 5 Introduction to Modeling Solutions 6 Top-Down Design Planning Methodology 7 Introduction to Physical Data 8 Quick Timing Models 9 Extracted and Interface Logic Models 10 Lab Conclusion Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Unit Objectives 7 -2 After completing this unit, you should be able to: n State why physical data is useful during top-level integration n State what is SDF data n State three parasitic models Prime. Time accepts n State the precedence of back-annotated data Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Why Use Physical Data? 7 -3 Why use. Quick physical data? Creating Timing Mode and its Application Introduction to physical data Models Advantages of Timing Resolve. Advantages some issuesofwith back-annotation Timing Models Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Timing Convergence n The goal is to achieve timing convergence with the physical tools l n 7 -4 Without timing convergence, there may be many iterations between the logical and physical tools before timing closure! Execute top-level integration with available physical data l Prelayout, timing analysis performed based on wire load models l Postlayout, replace wire load models with actual net parasitic data Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

The Limitation of Wire Load Models 7 -5 Logical Design Prime. Time assumes the circuit looks like this: b All nets (fanout = 1) except sel: length = 0. 39 (from wire load model) sel: (fanout = 2) length = 0. 86 (from wire load model) n 1 y sel a n 2 Physical Design Even though, after layout, it may look like this: b n 1 y sel a n 2 net a b sel length 0. 41 0. 90 net n 1 n 2 y length 0. 35 0. 97 0. 38 Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

The “Cost” of Estimating Net Delays n In large geometries, net delay was only a small portion of a path’s total delay l n 7 -6 Estimating the timing of a “low impact” portion of the circuit is OK In smaller geometries, delays due to net capacitance are a large portion of the path delay Unknown delay during compile Delay Inter conn Delay due to interconnect is up to 70% of the total delay ect d elay Cell delay 1. 0 Device gate length 0. 5 0. 2 Technology Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Introduction to Physical Data 7 -7 Why use. Quick physical data? Creating Timing Mode and its Application Introduction to physical data Models Advantages of Timing Resolve. Advantages some issuesofwith back-annotation Timing Models Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Parasitic versus SDF 7 -8 0. 02 0. 03 SDF 0. 02 Parasitics 0. 02 0. 08 n SDF back-annotation is used to describe net and cell delays l n n No cell or net delay calculation by PT - a “frozen” snapshot Parasitic back-annotation is used to describe net resistance and capacitance (RC). RCs are used for l Performing design rule analysis (for example, max_capacitance) l Computation of cell and net delays if no SDF is annotated Using SDF will be faster than delay calculation with parasitics l For multiple analyses on the same netlist, use PT to generate SDF for subsequent runs Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

report_timing with Physical Data 7 -9 report_timing now tags various symbols to indicate type of back-annotation information Symbol Annotation H Hybrid annotation * SDF back annotation & RC network back annotation $ RC pi back annotation + Lumped RC <none> Wire load model or none Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Back-Annotation Command Summary n n 7 -10 read_sdf l report_annotated_delay, report_annotated_check l remove_annotated_delay, remove_annotated_check read_parasitics l report_annotated_parasitics l remove_annotated_parasitics Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Parasitic Back-Annotation Third-Party Extraction Tools Chip Architect, Arcadia Parasitic Back. Annotation 7 -11 Prime. Time Timing Assertions Prime. Time Delay Calculator and Analysis RSPF/DSPF/SPEF Formats Timing Closure Tools Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Different Parasitic Formats 7 -12 n set_load/set_resistance -- Lumped RC Model n SPEF -- Standard Parasitic Exchange Format (IEEE standard) n RSPF -- Reduced Standard Parasitic Format n DSPF -- Detailed Standard Parasitic Format Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Lumped RC Data 7 -13 set_load 0. 08 [get_net Net. A] set_resistance 0. 12 [get_net Net. A] U 1 U 2 R = 0. 12 C = 0. 08 Net. A U 3 Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

More on Lumped RC data is the simplest model which PT accepts for back-annotated parasitics l n 7 -14 Entire net represented by a single capacitance and resistance Limitations: l Does not model varying load placement l Does not model net topology l Can be pessimistic Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

The Reduced RC Model 7 -15 read_parasitics my. Des. rspf Elmore delay from U 1 to U 2 r ive Dr U 1 C 2 (Cnear) U 2 R 3 R 1 C 1 (Cfar) E 1 + - C 3 s d a Lo R 4 E 2 + - C 4 U 3 Elmore delay from U 1 to U 3 Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

More on the Reduced RC Model n n 7 -16 The reduced RC model is more accurate than the lumped RC model l Net RC represented by the Pi model l Cnear and Cfar model varying load placement. R provides resistance shielding Limitations l Does not model net topology Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

The Detailed RC Model 7 -17 read_parasitics my. Des. dspf R 5 C 3 R 1 C 1 R 2 C 5 C 7 R 4 C 4 R 6 C 6 Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

More on the Detailed RC Model n n n 7 -18 The detailed RC data is the most accurate model PT accepts for back-annotated parasitics l Net RC represented by many Rs and Cs l Addresses net topology Limitations: l Consumes most CPU time l Requires iterative calculations for each net For more information read Delay Calculation with Detailed Parasitics, Appendix A in Prime. Time User Guide: Advanced Timing Analysis Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Parasitic Trip-Point Parameters 7 -19 Prime. Time environment variables have to be set to match the library characterization trip-points for SPEF/RSPF/DSPF The default values for the variables are: rc_input_threshold_pct_fall = "50" rc_input_threshold_pct_rise = "50" rc_output_threshold_pct_fall = "50" rc_output_threshold_pct_rise = "50" rc_slew_lower_threshold_pct_fall = "20" rc_slew_lower_threshold_pct_rise = "20" rc_slew_upper_threshold_pct_fall = "80" rc_slew_upper_threshold_pct_rise = "80" Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

List of Precedence 7 -20 If SDF and parasitic data are both annotated, the order of precedence for timing analysis is as follows: ÊSDF ËSPEF/DSPF/RSPF ÌLumped RC ÍWire Load Models Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Resolve Some Back-Annotation Issues 7 -21 Why use. Quick physical data? Creating Timing Mode and its Application Introduction to physical data Models Advantages of Timing Resolve. Advantages some back-annotation issues of Timing Models Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Missing Timing Arcs in SDF 7 -22 pt_shell> read_sdf AM 2910. sdf Error: No net timing arc from pin 'U 1/Z' to pin 'U 2/A'. (PTE-014) Error: Cannot find pin ‘U 10/CORE/Z’ in design AM 2910 (DES-002) n Suggestions l Check for out-of-date SDF l Arcs in SDF must match arcs in library and design l Check SDF hierarchy separator is consistent with netlist l Some SDF writers won’t write delays below a threshold u l PT will calculate delays. Check path prefix is correct u read_sdf -path u read_sdf -strip_path Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

List Missing Timing Arcs in SDF 7 -23 report_annotated_delay -list_not_annotated ******************** Report : annotated_delay -list_not_annotated Design : TOP ******************** Non backannotated NETS from input ports: --------------------1. CARRY_IN -> U 2/U 73/B 2. CARRY_IN -> U 2/U 102/B 3. CLOCK -> U 22/A. . | | | NOT |. Delay type | Total | Annotated | ---------------+-----------+------+ cell arcs | 1078 | 1065 | 13 | internal net arcs | 396 | 325 | 71 | net arcs from primary inputs | 44 | 0 | 44 | net arcs to primary outputs | 16 | 0 | 16 | ---------------+-----------+------+ | 1534 | 1390 | 144 | Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Incomplete RC Network for DSPF 7 -24 How does PT handle incomplete DSPF back-annotated nets? PT discards the detailed RC network data and uses the wire load model pt_shell> report_annotated_parasitics -check Error: Driver pin 'U 5/U 200/Z' is not connected to RC network of net 'U 5/n 529’ RC network on that net is incomplete, so it is ignored. (DES-026) Error: Load pin 'U 5/U 200/A' is not connected to RC network of net 'INSTRUCTION[3]' RC network on that net is incomplete, so it is ignored. (DES-026) Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Filling in Incomplete Net Parasitic Data n n 7 -25 PT can fill incomplete parasitics with the following conditions l The segments that have physical data are from DSPF or SPEF l The complete missing segment is between two pins, hierarchical and leaf or hierarchical and hierarchical Do not use to fix parasitic files with errors l Use only to fill the remaining, less significant segments of a net with zero or a wireload model read_parasitics spef_file. spef complete_net_parasitics [-complete_with zero|wlm] Missing Segments block. A U 1 OUT block. B IN U 2 Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Unit Review 7 -26 n State why physical data is useful during toplevel integration n State what is SDF data n State three parasitic models Prime. Time accepts n State the precedence of back-annotated data Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Lab Overview and Review LAB 45 minutes 7 -27 n Incorporate physical data into PT and perform STA n Explore the difference between parasitic data and SDF n Resolve one back-annotation issue Lab Review Why is it important to understand fix any missing physical data? When using an SDF flow for timing analysis, what will PT use for design rule checks (for example, max_capacitance or max_transition)? Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Plus! 7 -28 Additional Information. . . The information contained in the “PLUS!” section is intended to supplement the workshop material. Synopsys 37038 -000 -S 13 W 1 Introduction to Physical Data Synopsys Prime. Time Workshop

What Is Prime. Time-SI? n 7 -29 Extends Prime. Time’s ability to take into account the effects of crosstalk on timing l Crosstalk is a 1 st order problem for 0. 18 micron and below! n Based on proven STA technology n Crosstalk analysis throughout the design process + n Integration with implementation flow n Timing accurate Static Crosstalk Analysis n Low cost adoption n Multi-million gate capacity & performance Prime. Time-SI Static Timing Analysis STA Technology with Crosstalk Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

What Is Crosstalk? 7 -30 n The electrical interaction that occurs between two or more nets n Causes: Aggressor CS CW Victim l Long parallel net l Coupling capacitance l High frequency switching Delay Variation Aggressor Noise/Glitch Victim Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

What Are Crosstalk Delay Effects? n Timing failures l n 7 -31 Crosstalk affects interconnect delay of affected nets l Nets changing in the same direction: speed up l Nets changing in opposite directions: slow down STA tools model cross-coupling capacitances as grounded capacitance only! Volt Ideal waveform Speed-up Effect Slow-down Effect Switching Threshold Time Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

State of the Solutions Traditional Bolt on Analysis 7 -32 Static Crosstalk Analysis Synthesis Physical Synthesis Place & Route Static Timing Analysis SPICE Simulation Crosstalk Analysis Integrated Static Timing & Crosstalk Analysis Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

Detailed Standard Parasitic Format (DSPF) P R 0 C 0 P: 1 R 1 C 1 y A C 2 7 -33 *|DSPF 1. 3 *|DESIGN "counter" *|DATE "Fri Jun 11 11: 05: 06 1999" *|VENDOR "Synopsys, Inc. " *|PROGRAM "Prime. Time" *|VERSION "1999. 10" *|DIVIDER / *|DELIMITER : *|BUSBIT "[]”. SUBCKT counter +A +B +C +QA *|GROUND_NET VSS * *|NET P 6. 576586 p. F *|P (P I 0. 000000 p. F) *|S (P: 1 0. 0) *|I (y: A y A I 1. 000000 p. F 0 0) R 0 P P: 1 61. 728001 R 1 P: 1 y: A 61. 728001 C 0 P VSS 1. 858862 p. F C 1 P: 1 VSS 1. 858862 p. F C 2 y: A VSS 1. 858862 p. F Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop

RSPF Example *|RSPF 1. 3 *|DESIGN "counter" *|DATE "Fri Jun 11 11: 07: 35 1999" *|VENDOR "Synopsys, Inc. " *|PROGRAM "Prime. Time" *|VERSION "1999. 10" *|DIVIDER / *|DELIMITER : *|BUSBIT "[]". SUBCKT counter +A +B +C +QA *|GROUND_NET VSS *|NET b 1. 000000 p. F * *|DRIVER ffa: Q ffa Q *|S (b: 1 0. 0) R 1 ffa: Q b: 1 50. 000000 C 1 ffa: Q VSS 0. 057990 p. F C 2 b: 1 VSS 0. 102600 p. F *|LOAD QA: A QA A *|S (b: 2 0. 0) E 1 b: 2 VSS ffa: Q VSS 1 R 1 b: 2 QA: A 0. 000000 C 1 QA: A VSS 1 p. F Synopsys 37038 -000 -S 13 W 1 7 -34 Header info Port info Net name and Ctotal Driver, R 1, C 1, and C 2 Load Voltage, R and C Introduction to Physical Data Synopsys Prime. Time Workshop

Appendix: SDF & SPEF IEEE Format Specs n SPEF (Standard Parasitic Exchange Format) IEEE 1481 -1998 http: //www. eda. org/dpc-pandc/index. html n SDF (Standard Delay Format) http: //www. eda. org/sdf n Cadence l l 7 -35 DSPF (Detailed Standard Parasitic Format) RSPF (Reduced Standard Parasitic Format) Introduction to Physical Data Synopsys 37038 -000 -S 13 W 1 Synopsys Prime. Time Workshop