Stmt FSM Arvind with the help of Nirav

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Stmt FSM Arvind (with the help of Nirav Dave) Computer Science & Artificial Intelligence

Stmt FSM Arvind (with the help of Nirav Dave) Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -1

Motivation Some common design patterns are tedious to express in BSV n n Testbenchs

Motivation Some common design patterns are tedious to express in BSV n n Testbenchs Sequential machines (FSMs) w especially sequential looping structures These are tedious to express in Verilog as well (but not in C) March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -2

get. Token enter RAM yes done? no fifo out. Q cbuf get. Result Testing

get. Token enter RAM yes done? no fifo out. Q cbuf get. Result Testing the IP Lookup Design Input: IP Address Output: Route Value Need to test many different input/output sequences March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -3

Testing IP Lookup Call many streams of requests responses from the device under test

Testing IP Lookup Call many streams of requests responses from the device under test (DUT) Check correct with 1 request at a time Case 1 dut. enter(17. 23. 12. 225) dut. get. Result() dut. enter(17. 23. 12. 25) dut. get. Result() March 10, 2010 Check correct with 2 concurrent requests Case 2 dut. enter(128. 30. 90. 124) dut. enter(128. 30. 90. 126) dut. get. Result() http: //csg. csail. mit. edu/6. 375 L 11 -4

But we usually want more counters, display, . . . function Action make. Req(x);

But we usually want more counters, display, . . . function Action make. Req(x); action req. Cnt <= req. Cnt + 1; dut. enter(x); $display(“[Req #: ”, fshow(req. Cnt), “] = ”, fshow(x)); endaction endfunction Action get. Resp(); action res. Cnt <= res. Cnt + 1; let x <- dut. get. Result(); $display(“[Rsp #: ”, fshow(res. Cnt), “] = ”, fshow(x)); endaction endfunction March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -5

Writing a Testbench (Case 1) rule step 0(pos==0); make. Req(17. 23. 12. 225); pos

Writing a Testbench (Case 1) rule step 0(pos==0); make. Req(17. 23. 12. 225); pos <= 1; endrule step 1(pos==1); get. Resp(); pos <= 2; Wait until response is ready endrule A lot of text! March 10, 2010 rule step 2(pos==2); make. Req(17. 23. 12. 25); pos <= 3; endrule step 3(pos==3); get. Resp(); pos <= 4; endrule finish(pos==4); $finish; endrule How should we do it for a sequence of 100 actions? http: //csg. csail. mit. edu/6. 375 L 11 -6

A more complicated Case: Initializing memory addr 0 i n. I f(i) Need an

A more complicated Case: Initializing memory addr 0 i n. I f(i) Need an FSM in HW as memory can only do one write per cycle C int i; Addr addr=addr 0; bool done = False; for(i=0; i<n. I; i++){ mem. write(addr++, f(i)); } done = True; BSV Reg#(int) i <-mk. Reg(0); Reg#(Addr) addr <-mk. Reg(addr 0); Reg#(Bool) done <-mk. Reg(False); rule initialize (i < n. I); mem. write (addr, f(i)); addr <= addr + 1; i <= i + 1; if (i+1 == n. I) done<=True; endrule March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -7

Initialize a memory with a 2 -D pattern addr 0 j n. J Reg#(int)

Initialize a memory with a 2 -D pattern addr 0 j n. J Reg#(int) i Reg#(int) j Reg#(Addr) addr Reg#(Bool) done f(i, j) i n. I Bluespec code gets messier as compared to C even with small changes in C, e. g. , n n initialization based on old memory values initialization has to be done more than once Shall we do triply-nested loops? March 10, 2010 <-mk. Reg(0); <-mk. Reg(addr 0); <-mk. Reg(False); rule loop ((i < n. I) && (j < n. J)); mem. write (addr, f(i, j)); addr <= addr + 1; if (j < n. J-1) j <= j + 1; else begin j <= 0; if (i < n. I-1) i <= i + 1; else done <= True; endrule http: //csg. csail. mit. edu/6. 375 L 11 -8

An imperative view It is easy to write a sequence in C Writing this

An imperative view It is easy to write a sequence in C Writing this in rules is tedious: Can we just write the actions and have the compiler make the rules? March 10, 2010 void do. Test(){ make. Req(17. 23. 12. 225); get. Resp(); make. Req(17. 23. 12. 25); get. Resp(); exit(0); } seq make. Req(17. 23. 12. 225); get. Resp(); make. Req(17. 23. 12. 25); get. Resp(); $finish(); endseq; http: //csg. csail. mit. edu/6. 375 L 11 -9

From Action Lists to FSMs start done FSM interface FSM; method Action method Bool

From Action Lists to FSMs start done FSM interface FSM; method Action method Bool endinterface start(); done(); Creating an FSM module March 10, 2010 mk. FSM#(Stmt s)(FSM); http: //csg. csail. mit. edu/6. 375 L 11 -10

The Stmt Sublanguage BSV Action Stmt = Sequence of Stmt <Bluespec Action> List of

The Stmt Sublanguage BSV Action Stmt = Sequence of Stmt <Bluespec Action> List of Parallel Stmts | seq s 1. . s. N endseq | par s 1. . s. N endpar Conditional Stmts | if-then / if-then-else | for-, while-, repeat(n)Loop Stmts (w/ break and continues) March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -11

Translation Example: Seq to FSM Stmt s = seq make. Req(17. 23. 12. 225);

Translation Example: Seq to FSM Stmt s = seq make. Req(17. 23. 12. 225); get. Resp(); make. Req(17. 23. 12. 25); get. Resp(); $finish(); endseq; FSM f <- mk. FSM(s); March 10, 2010 module mk. FSM_s(FSM) Reg#(Bit#(3)) pos <- mk. Reg(0); rule step 1(pos==1); make. Req(17. 23. 12. 225); pos <= 2; endrule step 2(pos==2); get. Resp(); pos <= 3; endrule step 3(pos==3); make. Req(17. 23. 12. 25); pos <= 4; endrule step 4(pos==4); get. Resp(); pos <= 5; endrule step 5(pos==5); $finish; pos <= 0; endrule method Action start() if(pos==0); pos <= 1; endmethod Bool done() return (pos == 0); endmethod endmodule http: //csg. csail. mit. edu/6. 375 L 11 -12

Parallel Tasks seq ref. Req(x); ref. Res(r. Reg); dut. Req(x); dut. Res(d. Reg); check.

Parallel Tasks seq ref. Req(x); ref. Res(r. Reg); dut. Req(x); dut. Res(d. Reg); check. Match(r. Reg, d. Reg); endseq We want to check dut and ref have same result Do each, then check results But it doesn’t matter that ref finishes before dut starts… March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -13

Start ref and dut at the same time Seq. for each implementation Start together

Start ref and dut at the same time Seq. for each implementation Start together Both run at own rate Wait until both are done March 10, 2010 seq par seq ref. Req(x); ref. Res(refv); endseq dut. Req(x); dut. Res(dutv); endseq endpar check. Match(refv, dutv); endseq http: //csg. csail. mit. edu/6. 375 L 11 -14

What exactly is the translation? The Stmt sublanguage is clearer for the designer; but,

What exactly is the translation? The Stmt sublanguage is clearer for the designer; but, what FSM do we get? Let’s examine each Stmt Construction case and see how it can be implemented March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -15

Base Case: Primitive Action: a Reg#(Bool) done. R <- mk. Reg(True); rule dowork(!done. R);

Base Case: Primitive Action: a Reg#(Bool) done. R <- mk. Reg(True); rule dowork(!done. R); a; done. R <= True; endrule method Action start() if (done. R); done. R <= False; endmethod Bool done(); return done. R; endmethod March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -16

Sequential List - seq s 1. . . s. N endseq: sequential composition Reg#(int)

Sequential List - seq s 1. . . s. N endseq: sequential composition Reg#(int) s <-mk. Reg(0); What is FSM s 1 <- mk. FSM (s 1); … ; FSM s. N <- mk. FSM (s. N); wrong if we Bool flag = s 1. done() && … s. N. done(); just had this? rule one (s==1); s 1. start(); s <= 2; endrule two (s==2&& s 1. done()); s 2. start(); s <= 3; endrule … rule n (s==n && s. N-1. done()); s. N. start(); s <= 0; endrule method Action start() if (flag); s <= 1; endmethod Bool done(); return flag; endmethod March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -17

Implementation - par s 1. . . s. N endpar: parallel composition FSM s

Implementation - par s 1. . . s. N endpar: parallel composition FSM s 1 <- mk. FSM (s 1); … ; FSM s. N <- mk. FSM (s. N); Bool flag = s 1. done() && … && s. N. done(); method Action start() if (flag); s 1. start(); s 2. start(); …; s. N. start(); endmethod Bool done(); return flag; endmethod March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -18

Implementation - if if p then s. T else s. F: conditional composition FSM

Implementation - if if p then s. T else s. F: conditional composition FSM s. T <- mk. FSM (s. T); FSM s. F <- mk. FSM (s. F); Bool flag = s. T. done()&& s. F. done(); method Action start() if (flag); if (p) then s. T. start() else s. F. start(); endmethod Bool done(); return flag; endmethod March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -19

Implementation - while p do s: loop composition s <- mk. FSM(s); Reg#(Bool) busy

Implementation - while p do s: loop composition s <- mk. FSM(s); Reg#(Bool) busy <- mk. Reg(False); Bool flag = !busy; rule restart_loop(busy && s. done()); if (p) begin s. start(); busy <= True; else busy <= False; endrule method Action start() if (flag); if (p) begin s. start(); busy <= True; else busy <= False; endmethod Bool done(); return flag; endmethod March 10, 2010 http: //csg. csail. mit. edu/6. 375 what if this was replaced by busy <= True L 11 -20

The Stmt. FSM library This IS the Library (almost) n n Some optimizations for

The Stmt. FSM library This IS the Library (almost) n n Some optimizations for seq/base case Stmt syntax added for readability Good but not great HW (users can do better by handcoding) n state-encoding w Use a single wide register (i, j) instead of two w Use 1 log(n)-bit register instead of n 1 -bit registers w See if state can be inferred from other data registers n March 10, 2010 Unnecessary dead cycles can be eliminated http: //csg. csail. mit. edu/6. 375 L 11 -21

FSM atomicity FSM Actions are made into rules n rule atomicity governs statement interactions

FSM atomicity FSM Actions are made into rules n rule atomicity governs statement interactions Stmt s 1 = seq action f 1. enq(x); f 2. enq(x); endaction f 1. deq(); x<=x+1; endaction f 2. deq(); y<=y+1; endaction endseq; rule s 1(…); f 1. enq(x); f 2. enq(x); …; endrule s 2(…); f 1. deq(); x<=x+1; … endrule s 3(…); f 2. deq(); y<=y+1; … endrule Stmt s 2 = seq action f 1. enq(y); f 2. enq(y); endaction f 1. deq(); $display(“%d”, y); endaction f 2. deq(); $display(“%d”, x); endaction endseq; rule s 1(…); f 1. enq(y); f 2. enq(y); …endrule s 2(…); f 1. deq(); $display(“%d”, y); …endrule s 3(…); f 2. deq(); y<=y+1; …endrule March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -22

FSM Atomicity We’re writing actions, not rules n Do they execute atomically? Seq. Stmt

FSM Atomicity We’re writing actions, not rules n Do they execute atomically? Seq. Stmt Only one at a time Safe n Par. Stmt all at once What about conflicts? n par x <= x + 1; x <= 2 * x; x <= x ** 2; endpar What happens here? • rule p 1; x <= x + 1; …endrule • rule p 2; x <= 2 * x; …endrule • rule p 3; x <=x ** 2; …endrule Each rule happens once. Order is arbitrary March 10, 2010 http: //csg. csail. mit. edu/6. 375 L 11 -23

FSM summary Stmt sublanguage captures certain common and useful FSM idioms: n sequencing, parallel,

FSM summary Stmt sublanguage captures certain common and useful FSM idioms: n sequencing, parallel, conditional, iteration FSM modules automatically implement Stmt specs FSM interface permits composition of FSMs Most importantly, same Rule semantics n n n March 10, 2010 Actions in FSMs are atomic Actions automatically block on implicit conditions Parallel actions, (in the same FSM or different FSMs) automatically arbitrated safely (based on rule atomicity) http: //csg. csail. mit. edu/6. 375 L 11 -24

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