On the Limits of Leakage Power Reduction in

On the Limits of Leakage Power Reduction in Caches Yan Meng, Tim Sherwood and Ryan Kastner UC, Santa Barbara HPCA-2005

Overview l l Caches are good targets for tackling the leakage problem Much work has been done in this field • Gated-Vdd • [Powell 01], [Agarwal 02], [Roy 02], [Hu 02], [Kaxiras 01], [Zhou 03], [Velusamy 02] • Multiple supply voltages • [Flaunter 02], [Kim 02, 04], [Mudge 04] • Others • [Hu 03] , [Li 04], [Heo 02], [Hanson 01], [Li 03], [Bai 05], [Skadron 04], [Zhang 02], [Azizi et al. 03]

Research Question and Finding l What is the best leakage power saving we could hope to achieve with existing techniques? l Far more potential left for further reducing leakage power in caches

Outline l l l Motivation Definitions Optimal approach The generalized model Experimental results Conclusions

Motivation l Why to study leakage problem? • Leakage power: dominant source for power consumption as technology scales down below 100 nm Fig: Projected leakage power consumption as a fraction of the total power consumption according to International Technology Roadmap for Semiconductor

Motivation l Why to tackle the leakage problem through caches? • Caches : huge chip • area (50% 2005 [ITRS]) Major source for leakage power consumption Alpha 21364 microprocessor die photo [http: //www. oracle. com/technology/products/rdb/pdf/2 002_tech_forums/rdbtf_2002_opt_on_alpha_mdr. pdf]

Motivation l How to tackle the problem with existing techniques? • Keep frequently accessed cache lines active to ensure • • l high performance Turn off cache lines that are not used for a long time Use low supply voltage to save power for the rest What’s the best that the existing circuit and architecture techniques could achieve? How much room is left for further research?

Definitions – Cache Interval l Time between two successive accesses to the same cache line access(i) access(i+1) |Ii| Time

Definitions --- Operating Modes l Active mode • • Power on the whole cache line No power saving l Sleep mode [Roy 01, Hu 01] • Sleep/“turn off” transistors • Lose data • Refetch data with high overhead l Drowsy mode [Flautner 02, Mudge 04] • Use low supply voltage to save power when it is not needed • Preserve data for fast reaccess • Wake up to the high voltage and return data

Choosing Operating Modes |Ii| l l l Active mode Sleep mode Drowsy mode

Optimal Approach l Differences • Studying optimality • Combining all three modes to achieve the maximal leakage power saving l Optimal policy • Oracle knowledge of future address trace • Applying the appropriate operating mode on • • each cache interval Obtaining optimal leakage power saving Formal proof of the optimality

Inflection Points l l Which mode to apply on each interval? Active-drowsy inflection point a • The least amount of time drowsy mode needs to save energy l Sleep-drowsy inflection point b • The time where sleep and drowsy modes consume the same amount of energy

Selecting Operating Modes with Inflection Points a Active Interval Active Mode a<|I|≤b Drowsy Interval Drowsy Mode Sleep Interval Sleep Mode |≤ < |I 0 I |I|? |I|> b Optimality

Calculating Inflection Points l Active-drowsy inflection point a l Sleep-drowsy inflection point b CD

Saving Leakage Power without Performance Degradation l l Deriving the interval lengths with perfect knowledge of the future address trace Fetching any needed data just before it is needed Avoiding any performance impact Taking into account the power cost of just-in-time refetch CD

Saving Leakage Power without Performance Degradation Just before needed

The Generalized Model l Parameterized model • Inputs • • l • • Wake-up latencies Interval distribution Leakage power of each state Transition energy between states Outputs • EAS Optimal savings of OPT-Drowsy, OPT-Sleep, and OPT-Hybrid Can be extended to accommodate future technologies and power saving modes Publicly available • P(Active) http: //express. ece. ucsb. edu/software/leakage. html P(Sleep)

Methodology l l Core: Compaq Alpha 21264 [Kessler 99] • Memory • 2 -way L 1 instruction and data caches, 64 KB • Unified direct mapped L 2 cache, 2 MB • LRU replacement policy Tools • Sim. Alpha simulator • Hot. Leakage • Leakage power and dynamic cost • Parameters: taken from Hot. Leakage l Averaged results over all benchmark applications

Calculating Inflection Points • The sleep-drowsy point decreases from 180 nm to 70 nm • Because the leakage power consumption increases while the dynamic power consumption caused by an induced miss decreases • Our approach can be parameterized and applied to many • other memory technologies 70 nm, the most advanced technology, is used in the rest of our study

Exploring the Upper-bound OPT-Sleep(10 K) OPT-Drowsy Sleep(10 K) OPT-Hybrid No Turning performance Optimally off cache combining penalty lines after with forthree waking lengths 10 Kmodes cycles up greater data w/o [Hu 01] than performance 10 K cycles penalty OPT-Drowsy Sleep(10 K) OPT-Sleep(10 K) L 1 data cache OPT-Hybrid

Research Finding l l l Larger leakage saving can be achieved for data cache Drowsy and sleep modes each achieve fairly high savings Savings are complementary: potential in combining drowsy and sleep technologies

Conclusions l Why leakage? • • l l Leakage: dominant source of power consumption as technology scales down below 100 nm Caches: primary targets to tackle the problem Optimal approach and software • • • Calculating the maximal leakage savings Quantifying how much room left for improvement Used to guide future power management policy research Great potential in combining techniques • • Optimally combining Active, Drowsy, and Sleep The optimal approach reduces power dissipation • Instruction cache: by a factor of 5. 3 • Data cache: by a factor of 2