Multiscalar Processors Andreas Moshovos moshovoseecg toronto edu EA
- Slides: 23
Multiscalar Processors Andreas Moshovos moshovos@eecg. toronto. edu EA 310 A. Moshovos Fall 2010 – ECE U. of Toronto
Conventional In-Order Processors • Sequential Fetch-Execute Paradigm – Instructions execute in “program order” • Latency is king • Total Execution Order A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
OOO Processors • Performance from Concurrency – Do as many things in parallel as you can • OOO Processors – Partial execution order: dependencies • Want higher performance? – Build larger window – Find more parallelism • Challenge? – Control Flow Instructions A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Control Flow Walk: Conventional OOO • Fetch in-order • Predict in-order • If accuracy is X possibility of correctly predicting N branches is X^N – Drops rapidly Prediction Accuracy? • How about this? A B Prediction Accuracy? A. Moshovos © Prediction Accuracy? C ECE 1773 - Fall ‘ 07 ECE Toronto While (cond) if (cond 2) THENPART OTHER
Multiscalar Control Flow Graph Walk Conventional A B C • Goal: – Establish large and accurate window A. Moshovos © Multiscalar A A B B C C A B C ECE 1773 - Fall ‘ 07 ECE Toronto
Multiscalar CFG walk • Not instruction-instruction • Not Basic-Block task • Hierarchical: – Task-Task – Instruction-Instruction • Task? – Portion of the CFG – Execution corresponds to contiguous region of the dynamic instruction sequence • • • Part of basic block Sequence of basic blocks Loop iteration Loop Function call A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto Not a task
Possible Microarchitecture inner A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto outer
Multiscalar Execution A A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto B C
A More Detailed View of Multiscalar A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Maintaining Sequential Semantics • Two fold strategy – Within each unit • Maintain sequential semantics as a conventional processor would – Across Units • Organized into a ring • Ordering is maintained using head and tail pointers A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Another Example (Manoj Franklin’s thesis) A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Comparison with VLIW – Uncertain Stalls? A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
An example Program A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Multi-version register file A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Multiscalar Programs A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Scott Breach et al. , Anatomy of the Multiscalar Register File A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Memory Renaming A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Detecting Violations/Forwarding Values A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Detecting Violations/Forwarding Values A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Revisit Conventionally Held Assumptions • Branch Prediction accuracy must limit ILP • A wide window of pending instructions requires the complexity of concurrently monitoring the issue state of all individual instructions in this window • To issue n instructions simultaneously, there must be logic of n^2 complexity to perform dependence cross checks among the instructions • All loads and stores must be identified and the referenced addresses must be computed, before memory accesses can be reordered A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
Instruction Counts A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
A. Moshovos © ECE 1773 - Fall ‘ 07 ECE Toronto
