Digital System Design Verilog HDL Introduction to Synthesis
- Slides: 10
Digital System Design Verilog® HDL Introduction to Synthesis: Concepts and Flow Maziar Goudarzi
Objectives • Learn – What is synthesis – Understand appreciate differences between simulation and synthesis – Various synthesis tools – Get ready for the course laboratory and learn its limitations 2010 DSD 2
Logic Synthesis? Why? • Assembly coding vs. C/Java programming • Gate-level modeling vs. behavioral modeling 2010 DSD 3
Logic Design Course • Standard products – Adders 2010 DSD 4
Traditional Logic Design Flow 2010 DSD 5
Logic Synthesis Flow 2010 DSD 6
Logic Synthesis • Process of generating detailed logic gates from higher-level description – RTL (Register Transfer Level) / Logic Synthesis – Behavioral Synthesis (High Level Synthesis) • Decide number of registers and their interconnects in addition to RTL synthesis 2010 DSD 7
Verilog Lower Abstraction Levels • Gate Level Models – All synthesizable • Dataflow Models – Most expressions synthesizable – Exceptions: *, /, %, ===, !== • General rule – Delays are all ignored 2010 DSD 8
Behavioral Level • General rules – All delays ignored – initial blocks not synthesizable – always statements • Sensitivity list decides what is synthesized • Further details: later in this semester, after ASIC and FPGA internal structures are taught 2010 DSD 9
Famous Synthesis Tools Company Famous Synthesis Tool (or design environment) Mentor Graphics Leonardo Spectrum Synopsys Design Compiler, Synplify Cadence Encounter RTL Compiler, Build. Gates Altera (FPGA company) Quartus Xilinx (FPGA company) ISE . . . The list continues… 2010 DSD 10
